I have 5 V coming in from a USB power bank to an LDO voltage regulator that drops it down to 3.3 V. On the 3.3 V line I have several ICs and IR sensors. One of the IR sensor consumes quite a bit of current in short bursts (I have a 10 µF cap across it).
Whenever that power hungry IR sensor turns on, it causes some other parts of my circuit to behave oddly for a split second. I figured adding a large capacitor to the 3.3 V rail would help eliminate that, which it did. But I also noticed that I could instead add a significantly smaller capacitor on the 5 V side, and that also solved the problem.
Why is it that the capacitor is more effective on the input side of the regulator rather than the output? I figured the charge would be "more readily available" to the system if it was on the output/3.3 V side, where the sensor is.
(I just tinker with electronics and have no formal knowledge beyond basic physics E&M.)
*Edit: Before the problem/experimentation I already had on either side of the regulator a 0.1uF cap, a 1uF cap, and two 10uF caps (totaling 21.1uF on either side). I began to add extra caps after the problem.
Best Answer
The voltage drop during a transient at the utilization point is roughly composed of the following:
inductance of the wire and the source before the regulator. In case of a typical system that uses long and thin power supply cable this is usually significant because the inductance of the cable is high.
inductance of the wire/PCB track after the regulator. This is usually short if the utilization is near the regulator but may be significant if the system uses a big PCB or perhaps more interconnected PCBs.
response time of the regulator. There are two major events that the regulator should respond to: input voltage variations, output load variations. These parameters can be found in its datasheet.
During a transient at the output of the regulator, the following happens:
If the input capacitor can not hold enough charge until it is filled back by the source the voltage drops below the regulator's minimum allowed input voltage. The regulator can not do anything: the output voltage remains below the nominal level until the input reaches the minimal level.
Forcing the regulator out of its designed operating region may have other serious drawbacks. If the originally closed loop control opens, the pass device may saturate. It is also possible that the input voltage is not enough to reliably power the internal circuitry and the device may shut down due to undervoltage lockout functionality or just not work properly. The recovery time from these situations may be much longer than the typical load response when there is enough input voltage. You should avoid this happening.
This can occur even if the output capacitor is large. The voltage across it will drop, and the regulator senses and tries to keep the output voltage and fill it back. If the cap is too large, the regulator will pull high current from the input side. The first problem is that it comes from the input capacitor so even if you have a large cap at the output the above situation can occur. The second problem is that it is possible that the current may be high enough to trigger the overcurrent protection which in itself slows down the response plus the recovery from overcurrent may be slower than the load regulation time. You should keep the regulator in normal operating conditions to achieve the best performance.
The output capacitor should be as small as possible, just enough to bridge the time when the regulator responds and compensates for the increased load. Roughly speaking, if you increase the output cap you just hardening the work of the regulator.
The best real-world approach is to start with a sufficiently large cap on the input side and a small one on the output side. Read the datasheet for recommendations. Check the transient on the output side with an oscilloscope. If it is not satisfactory, try increasing the output cap or replacing it with one that has a lower series inductance. Then examine the transient at the input and try to reduce the input cap. Keep some safety margin at both sides.
EDIT:
The impedance of the wire/PCB track after the regulator...
...has the same effect mentioned before: during transients or also in case of continuous but high frequency loading, at the utilization point there will be voltage notch (or continuous drop). If you compare the signal with an oscilloscope at the output of the regulator and at the utilization point, you will see that at the regulator there will be much smaller noise.
The inductance of the wire/track combined with the capacitor at the output of the regulator is an LC low-pass filter, effectively dampening the HF components.
This is good, because the noisy load does not distort the voltage of the regulator (too much). You can supply the MCU or other (analog) circuits all independently from the regulator in a star topology. This will effectively reduce the interference. If the track's inductance is not high enough, you can deliberately include inductors in the line. This can be seen often in equipments similar to yours: high power transient loads combined with sensitive analog/digital control.
High supply impedance is also bad, because you want smooth supply on every load, but this can be fixed with adding (low-ESR) capacitors to every utilization point. If you examine a PC motherboard for example, you will see hundreds of ceramic caps everywhere for that very reason.