Electrical – Why is DC component ignored and AC analysis is used when obtaining input output impedance of a BJT transistor amplifier

The "gain" formula as given by you is the transconductance of a transistor in common-emitter configuration WITH feedback.

1.) Without feedback (RE=0) this transconductance is simply $$gm = \frac{hfe}{hie}$$

2.) With feedback we have $$A= \frac{gm}{1+gm*R_E}= \frac{hfe}{hie+R_E}$$

From this, we can derive the loop gain Aloop=-gm*Re. Note that gm=hfe/hie.

3.) Based on the loop gain expression (and knowing that the output resistance will be increased using feedback) we can expect (approximation):

$$Z_{out}= Z_o*(1+gm*R_E)=r_{ce}*(1+gm*R_E)$$

4.) Comment: The above expression for Zout is an approximation because it is derived under the assumption of IDEAL voltage feedback. However, the feedback voltage is provided across RE (not an ideal voltage source). More than that, also the influence of the input circuitry was neglected. However, we should not forget, that during practical operation of this circuit the large value of Zout is paralleled with the collector resitor Rc (which is much smaller that Zout). Hence, the approximation seems to be acceptable.

In general

The output impedance of an amplifier is equivalent to a source impedance \$Z_{S}\$ from the perspective of a load with impedance \$Z_{L}\$. Think of a voltage divider where \$V_{\text{out}}\$ is the output voltage of the amplifier without a load (i.e. \$Z_{L} = \infty\$):

^{simulate this circuit – Schematic created using CircuitLab}

The voltage delivered to the load is

$$V_{\text{load}} = \frac{Z_{L}}{Z_{L} + Z_{S}}V_{\text{out}}$$

If \$Z_{S} \gg Z_{L}\$ then \$V_{\text{load}} \approx 0\$, which is bad if you are trying to amplify a voltage for the load. But if \$Z_{S} \ll Z_{L}\$ then \$V_{\text{load}} \approx V_{\text{out}}\$.

For voltage amplification you want low output impedance from the previous stage and high input impedance from the next stage to maximize the voltage gain.

For current amplification you want the reverse: high output impedance from the previous stage and low input impedance from the next stage. Think of a current divider: the current will mostly flow through the lower impedance, so a low input impedance from the next stage means most of the current will flow into the load.

Your case

\$R_{C}\$ actually forms part of the load for the common emitter -- the total load to the common emitter is \$R_{C} \| R_{L}\$ where \$R_{L}\$ is the input impedance looking into the load. As in the general case you want to maximize the input impedance looking into the next stage, so you want to maximize \$R_{C}\$. In the limiting case where \$R_{S} = \infty\$ the only load is the input impedance looking into the load (i.e. \$R_{L}\$), which is the maximum load impedance you can get. In the limiting case where \$R_{C} = 0\$ the collector is shorted to \$V_{CC}\$ and there can be no voltage gain (the collector, which is the output node, is just shorted to the supply).