I am facing an error while practicing a reference design of DLP-2232M-G board downloaded from Mentors website.
After I made schematic in PADS logic and connect with PADS layout, I found GND trace exists on PADS layout design.
Take a look, 2 capacitors ends are shorted, they should be "GND". In this design, no layer for "GND" has been called.
If you feel any setting is necessary in "Design rules", let me know.