I'm finding difficulty in understanding how the propagtion delay of this full adder is calculated in this primitve manner. Please see the following attached:
1) Lecture slide explaining worst case delay
2) Past Exam Question to calculate delay
3) Past Solution to exam question
For exam question (d, part i), I am still unsure how the answer is still 3 gate delays. I know S3:0 has changed from 0101(5) to 0110(6), more particularly bit S0 has changed from 1 -> 0 and bit S1 has changed from 0 -> 1. Bits S3 and S2 have remained the same.
Could you please walk me through which path was taken to calculate it's worst case delay (i.e 3 gate delays in this case)?
Many Thanks
Best Answer
Initially your carry outs are as follows
\$C_0 =0\$
\$C_1 =0\$
\$C_2 =0\$
\$P @ t=0\$ is '001'
\$P_0=1\$
\$P_1=0\$
\$P_2=0\$
At t=1 it becomes '010' as in
\$P_0=0\$
\$P_1=1\$
\$P_2=0\$
\$Q=4 => '100'\$ so if we were to look at the additions at the carry outs they do not change.
Since you are adding You are going from
\$P_0+Q_0=0+0=0 \rightarrow C_0=0\$ (No carry change )
\$P_1+Q_1=1+0=1 \rightarrow C_1=0\$ (No carry change)
\$P_2+Q_2= 0+1=1 \rightarrow C_2=0\$ (No carry change)
Since there are no carries the result of each adder goes to straight to the sum and there are no interactions between the adders since all your carries unchanged throughout the transition.
It takes 3 gate delays to get from Input of a value(Q or P) into the adder to the output(S or C) of it hence the answer is 3 gates.