I'm working on integrating an eMMC ship to a FPGA.
As for now, the initialization is working fine, I've managed to receive the CSD and CID registers properly, and I can select and move the chip to Transfer State.
The way my design is built, I have to send data to the FPGA from the MCU, that can then be forwarded for programming into the eMMC.
My question is, how am I supposed to do that properly, what is the good design pattern for this? Some kind of buffered FIFO?
The MCU/FPGA communication being serial, in order to have a full byte to send I need 8 SPI clock cycles, while I need only 1 MMC's clock cycle to send it to the MMC, its link being parallel. And I can't make the MMC wait for the next byte to be ready, otherwise I'll just be programming the previously set bits for the amount of mmc's clock cycles needed for the next byte to be received.
The FPGA clock is 12MHz, SPI's is 1.5MHz, MMC's is tuneable up to 12MHz.
A full block of data is 512 bytes, that's a logic vector of 4096 bits that I'm guessing I shouldn't allocate as a buffer, right?
Best Answer
You'd want some sort of byte-orientated fifo, preferably in a block RAM in the FPGA. Then only start the transfer to EMMC once the fifo is part-full.
Then you have to design the system to tolerate this stall in a sensible way and not leave incomplete blocks. Wait for 512 bytes, start writing it (accumulating more bytes in the meantime), then see if there's another block ready to be written