Could be this stack-up correct/appropriate for a 14 layer pcb?
The PCB includes a CPLD at 50 MHz and a Gigabit Ethernet transceiver at 125 MHz. Both mounted in Primary Component Side.
There are 4 different voltage.
Layer 7 is a non-splitted main power plane.
Layer 8 is a splitted power planes with three differents voltages.
Any suggestion with the prepeg thickness? IMHO, It will be better if the High Speed Signals are closer to the GND power and further between then.
Units are microns