Apart from noticing that maybe the integral in the average inductor current at the end of the second time period should (maybe?) run from D1 to D2 rather than 0 to D2 (but I might be wrong), I have an observation ...
... this sort of algebra-heavy approach may be correct, but I don't think it's useful.
My approach, which may be too approximate for some people, is biassed more towards understanding what happens, rather than any numerical or analytic precision.
Unless the boost converter is to be used open loop with fixed on and off times (rarely the case, and then only for relatively poorly regulated applications), the on and off times will be controlled by feedback from the output, to give you the correct voltage. So it doesn't matter exactly what the output voltage is for any specific D1 and D2, only that the converter stay within the correct range for operating.
First approximation, lose RL. It's only a loss term. If it becomes significant, you have a very lossy converter and should use a better inductor.
First vital restriction which doesn't appear in your analysis. The inductor will have a maximum current before it saturates. To keep the current below max, assuming DCM where the current starts from zero, always keep the ON time, subinterval 1, less than \$t_{max} = \dfrac{I_{max}L}{Vin}\$ . This will avoid the current growing beyond the maximum. It's a bit of an over-estimate, as it neglects RL, but that's on the conservative side, so it's good.
Change in capacitor voltage. That's easiest to do by equating energy. If we are doing DCM, then the current will drop to zero, and all the inductor energy will be transferred to the capacitor, along with the energy delivered by the supply during that time. Approximation - neglect the change in capacitor voltage to find that time, assume the current changes linearly (still neglecting RL), so \$t_{rundown}=\dfrac{I_L L}{VC-V_{in}}\$ It may well be worth including the voltage drop across D1 here, which I notice you've ignored at this point, but if the output voltage is high, then ignoring it is good.
And so it goes on, making judicious approximations, and having simple forumlae.
Right at the end, I might compute power lost in RL at the currents I've predicted, and see whether that's reasonable within my loss budget, or whether it needs a better inductor.
That's how I'd do it. Less exact than wall to wall equations, but at least I'm can see what I'm doing. It will allow me to see whether my L has adequate Imax, the clock rate is right for the ripple and output cap value etc.
No, you have it right so far. \$v_L\$ is equal to \$V_g\$ for the first part of the cycle and \$V_{out}\$ for the second part. So your volt-seconds balance equation ends up being:
$$DV_g + (1-D)V_{out} = 0$$
The negative sign comes out of the algebra you do to isolate \$V_{out}\$ on one side of the equation.
UPDATE: Sign convention doesn't really tell you anything about the physical voltage, it just determines the signs in your equations. If you invert the polarity of \$v_{out}(t)\$ in the schematic, your volt-seconds equation becomes:
$$DV_g - (1-D)V_{out} = 0$$
and \$V_{out}\$ will be "positive". But \$V_{out}\$ didn't really change -- the lower potential is still at the top node; you just defined that to be "positive"! In your graph, the inductor voltage will be positive for one part of the cycle and negative for the other. You can choose which is which by defining the polarity, but they'll always be opposite.
UPDATE 2: You asked how we get a negative voltage. Start with the volt-seconds balance equation:
$$DV_g + (1-D)V_{out} = 0$$
Solve for \$V_{out}\$:
$$V_{out} = -\frac{D}{1-D}V_g$$
So if \$V_g\$ is positive, \$V_{out}\$ will be a negative number. The sign convention tells you that a negative \$V_{out}\$ means the potential is lower at the top of the resistor and higher at the bottom.
Now, let's say you define \$V_{out}\$ the other way:
simulate this circuit – Schematic created using CircuitLab
During the second part of the cycle, the inductor is connected to the output, and you get:
$$v_L(t) = -V_{out}$$
In the volt-seconds balance equation, this becomes:
$$DV_g - (1-D)V_{out}$$
Solving for \$V_{out}\$ now gives you:
$$V_{out} = \frac{D}{1-D}V_g$$
and if \$V_g\$ is positive, \$V_{out}\$ will be a positive number.
Both of these approaches give the same result -- the buck-boost converter inverts the input voltage. It's just a question of whether you say that in the schematic or in the number.
Why do it the way your schematic does? Because it means the output voltage is defined the same way for different kinds of converters.
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