Electronic – 3-pin MOSFET: P or N type

Wiki says...

In a depletion-mode MOSFET, the device is normally ON at zero gate–source voltage. Such devices are used as load "resistors" in logic circuits (in depletion-load NMOS logic, for example). For N-type depletion-load devices, the threshold voltage might be about –3 V, so it could be turned off by pulling the gate 3 V negative (the drain, by comparison, is more positive than the source in NMOS). In PMOS, the polarities are reversed.

So for a depletion-mode PMOS it is normally ON at Zero volts but you need 3V or more on the gate higher than the supply voltage to turn OFF. Where do you get that voltage? I think , that's why it is uncommon.

In practise now we call them High Side Switches or Low Side switches for power MOSFETs. They prefer not to combine enhancement and depletion mode in the same chip as the processing costs are almost double. This patent defines some innovation and better physical desc. than I can remember. http://www.google.com/patents/US20100044796

It is possible though what you are suggesting and performance are key issues. However when it comes down to low ESR, MOSFETS are like voltage controlled switches with ESR changing over a wide range of DC voltages unlike bipolar transistors which are 0.6 to < 2V for max peak in some case. Also for MOSFETs it is constructive to think of them as having an impedance gain of 50 to 100 when looking at loads and ESR of source. So consider you need a 100 ohm source to drive 1 ohm MOSFET and 10 ohm source to drive a 10mΩ MOSFET if you use 100:1, Conservative is 50:1. This is ONLY important during the transition period of the switch, not the steady state gate current.

Whereas bipolar hFE drops dramatically so you consider hFe of 10 to 20 good when saturated for a power switch.

Also consider that MOSFETS as charge-controlled switches during transition, so you want to have a big charge available to drive the gate capacitance and load reflected into gate with a low ESR gate drive, if you to make a fast transition and avoid commutation ringing or bridge cross-over shorts. But that depends on design needs.

Hope that isn't too much info and the patent explains how it works for all modes of P N type depletion and enhancement in terms of device physics.

The Source and Bulk do not have to be connected.

In power devices, and especially in discrete transistors, the S & B are built very close together and shorted. This improves the breakdown voltage performance of the transistor.

In an IC, in some CMOS processes, the B of NMOS devices is always substrate (ground), and so in structures such as NOR gates which have 2 NMOS in series, the 2nd NMOS doesn't have the S=B.

Generally performance (gm, current) is better with S=B, but some technologies don't allow the B to be separated from the substrate for NMOS devices. PMOS devices in an IC generally can have separate S & B connections.

If you connected the B of PMOS to GND, you would have a parasitic diode from S to B (GND), and so your supply would be shorted (unless you wanted to run on a very low supply voltage of << 0.6 V). Some very low voltage circuits do use this technique.

A MOSFET connected as a diode will generally have worse performance than a PN junction in terms of the 'sharpness' of the curve. However, FETs with low threshold voltage (say 0.4 V or lower) will turn on at a lower voltage than a diode will, and this can be useful in low voltage circuits. For the same reason that the B is always substrate in some CMOS ICs, there isn't the flexibility to use a PN junction as a diode in all circuit configurations. If the PN junction of a PMOS is used (P = Source, N = Bulk), then there are some additional parasitics that need to be considered that make this not useful generally.