Electronic – 4-bit Finite State Machine with 6 states and synchronous reset using D Flip-Flops

flipflopkarnaugh mapstate-machines

I have recently began studying Digital Electronics and have hit a wall trying to figure out how to design FSMs. At the moment, I am attempting to desing the FSM in the title which generates the following states: 1101->1011->0111->0101->0011->0010. Am I right in saying that this is a Moore machine and there will be 4 DFFs in this circuit? And what are the inputs for the circuit?

I now need to create the Karnaugh maps and this is where I am really stuck. I understand K maps and can create them, but I don't understand how you determine how many K maps are needed, and what goes in the x-axis and y-axis of the K maps when designing an FSM?

Here is what I have come up with so far:

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EDIT

3rd bit Karnaugh Map:

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Best Answer

Based on your state diagram and explanation, you have everything you need there.

For every register (you have 4), you need to create a Karnaugh Map which determines what value will be clocked onto that register in each clock cycle.

The next value for each state register will depend on the current state as a whole (i.e. all state registers), and any other inputs (in your case only reset). So build your Karnaugh Map using those inputs.

Each of your states has a 4-bit value (e.g. your starting state is 1101). So you will need 4 registers to hold the value indicating current state. So for example lets call your state registers \$\left(S_3, S_2, S_1, S_0\right)\$, where the starting state would be say \$S_3=1\$, \$S_2=1\$, \$S_1=0\$, and \$S_0=1\$. Also lets call the reset signal \$R\$.

You will have maps which look something like:

$$ \begin{array}{c c c| cc} S_0 & & R & 0 & 0 & 0 & 0 & 1 & 1 & 1 & 1\\ & & S_3 & 0 & 0 & 1 & 1 & 1 & 1 & 0 & 0\\ & & S_2 & 0 & 1 & 1 & 0 & 0 & 1 & 1 & 0\\ S_0 & S_1 & \\ \hline 0 & 0 & & & & & & 1 & 1 & 1 & 1\\ 0 & 1 & & 1 & & & & 1 & 1 & 1 & 1 \\ 1 & 1 & & 0 & 1 & & 1 & 1 & 1 & 1 & 1 \\ 1 & 0 & & & 1 & 1 & & 1 & 1 & 1 & 1 \\ \end{array} $$

I've been exceedingly nice and filled in the map for \$S_0\$ for you based on your next state table. I'll let you make and fill in the other three maps.

Once you have your four maps you know the logic for each of the state registers.