You can't use the main timing resistor and capacitor to generate your trigger signal. As you discovered, this is exactly equivalent to the astable configuration.
Instead, you need to provide a separate resistor (to Vcc) and capacitor (to ground) for the Trigger pin. The time constant for this pair should be short relative to the main timing period, but long relative to the risetime of the power supply.
These components will hold the trigger low while the chip powers up, but then allow it to go high a short time later. Once the timer has timed out, the main timing capacitor will be discharged, but the trigger capacitor will not.
It takes almost 2 mA just to charge and discharge the gate of your MOSFET. You're also wasting about 5 mA in R1, since it is grounded through pin 7 about half the time. Your voltage feedback divider is drawing about 1 mA from the high-voltage rail, which translates to more than 20 mA at the input.
There's a problem with using a 555 to drive a large MOSFET: The limited output current of the 555 means that the MOSFET can't switch quickly from full-off to full-on and back again. It spends a lot of time (relatively speaking) in a transition region, in which it dissipates a significant amount of your input power instead of delivering that power to the output. The MOSFET has a total gate charge of 63 nC, and the 555 has a maximum output current of about 200 mA, which means it takes a minimum of 63 nC / 200 mA = 315 ns to charge or discharge the gate. If you're using a CMOS 555, the output current is much less and the switching time is correspondingly longer.
If you add a gate driver chip between the 555 and the MOSFET (one that's capable of peak currents of 1-2A), you'll see a marked increase in overall efficiency. A real boost controller chip will often have such drivers built in.
If you're serious about developing switchmode power converters, you definitely need to get an oscilloscope so that you can see these effects for yourself.
That regulator design is also rather crappy for another reason. The power through a boost mode converter is regulated by varying the duty cycle of the switching element. In this circuit, the feedback is created by using a transistor to pull down on the control voltage node of the 555, which reduces the upper switching threshold. However, because of the way the 555 is constructed, this also reduces the lower switching threshold by a proportional amount. This means that the change in duty cycle as the ouptut voltage rises is much less than you might otherwise think. It has a bigger effect on the frequency of the output pulses, but this isn't relevant. Again, switching to a proper boost controller chip would solve this problem.
By the way, the "regulator" part of the circuit is NOT using the input voltage as its reference, it's using the forward voltage of Q1's B-E junction as its reference.
As Spehro points out, a 100 µH inductor at a switching frequency of 30 kHz — nominal on time = 16 µs — with a 9V source is going to reach a peak current of 1.44 A. This is really abusing the hell out of a 9V battery, not to mention the I2R losses in both the inductor and the MOSFET. This is also uncomfortably close to the saturation current of the inductor, which only exacerbates the losses.
Best Answer
When the cap is discharged, you are in a situation similar to this:
simulate this circuit – Schematic created using CircuitLab
Since the cap is discharged, it is initially at zero volts. So what is the voltage at pins 6 and 2? Zero.
Of course, this starts changing as soon as current starts flowing into the cap. At first, all the voltage is dropped over the resistors, but as the cap starts to fill up, its terminal voltage starts to rise from zero. Now less and less current is flowing over the resistors, therefore less and less voltage is being dropped by them. Eventually the voltage across the cap (and therefore on pins 2 and 6) is high enough to trigger the comparators.
Think of it this way: The voltage can't get from the power rail to pin 2 or 6 without passing current through the resistors. Ohm's law tells us that current through a resistance drops voltage.
Let's look at the case when the capacitor has just finished discharging:
Image Source
Let us agree that when the capacitor is discharged, there is the same voltage on both its terminals. Let us also agree that the voltage seen at pins 2 and 6 is the same as the 'top' of the capacitor.
Now the capacitor starts charging as current flows from the 5 V source, through the resistors, and into the capacitor. Since this current is limited by the resistors, the rate at which the capacitor fills is called its RC time constant. i.e. This voltage rise is defined by the size of the resistors and the capacitance.
As the capacitor fills up, the voltage on the upper terminal starts to rise from ground. Remember, whatever voltage this terminal is at is the voltage that pins 2 and 6 are seeing.
Eventually this voltage is high enough to trigger the comparators, and the discharge pin gets grounded and discharges the capacitor, and now the whole thing starts over.