Electronic – 6-channel piezo buffer jfet circuit

I would like to know if it is possible to produce an n-channel jfet connected in fixed bias configuration with a high gain of 200.

For your circuit, the product of the small-signal transconductance and drain impedance at the operating point set an upper bound on the voltage gain.

Using the numbers @Andy aka provides:

\$A_v < 20k\Omega \times 6.5 \frac{mA}{V} = 130\$

Since your drain resistor and load are in parallel with the small-signal drain impedance, your circuit gain must be less than this upper bound.

So, as a first step, you must select a transistor with maximum possible voltage gain quite larger than 200.

A JFET is a P-N junction. Normally, reverse-biasing this P-N junction is what results in the high gate impedance. If you reverse bias it enough, the depletion region extends all the way across the channel, turning the transistor off.

Review the basic physical structure of a P-channel JFET:

Just an N-type gate stuck in a P-type channel. A P-N junction: that's a diode. A P-channel JFET is basically a diode that has a long anode with a connection on each end.

Your circuit forward biases the P-N junction. Thinking of the JFET as a P-N junction making a diode, we can redraw your circuit like this:

^{simulate this circuit – Schematic created using CircuitLab}

Do you see the problem now? When you close the switch, J1 is forward biased. Current driven by V1 can flow through SW1, R3, J1, and R2. Because there's current in R2, you see a voltage (think Ohm's law). When you increase the source resistance (and it's hard to say which you mean because the symbol is symmetrical, but I'm guessing R3) then you limit the current. Being there less current in R2, the voltage decreases.

To make this work, the gate should be connected to the + side of V1, not the - side. This will keep the gate reverse biased. The JFET will be on when the voltage from the gate to the source is 0V. To get the JFET to turn off, you must raise the gate to an even higher potential reverse biasing the P-N junction more, thickening the depletion layer, pinching the channel shut.

Try this (adjust V2 to be appropriate for the pinch-off voltage of whatever JFET you have):

^{simulate this circuit}