I'm working on a flash chip "W25Q128BV". I get really confused on the operating frequency of this chip.
As we can see, "Read Data" instruction is comprised of 3 steps for master: sending opcode, sending address, and reading data from flash.
My question is that can I use 104MHz for sending opcode or address? I think master must use clock frequency below 33MHz for reading data.
And I have the same question for Quad SPI and Dual I/O instructions. The datasheet says the max frequency for them is 70MHz. Taking instruction "Fast Read Quad Output(6bh)" for example, 
this instruction is comprised of 4 parts: sending opcode, sending address, sending dummy clocks, reading data. What is the max frequency of dummy clocks, 70MHz or 104MHz? What is the max frequency for sending opcode and address, 70MHz or 104MHz?
I have spent lots of time for this question on Google, but I couldn't find similiar questions and answers. I found that most people use a low frequency to control spi flash such as 30MHz. So they don't need to worry about the max frequency of a particular instruction. For some purpose, I have to operate this flash chip as fast as possible.
What's more, I also read some datasheets of similiar flash chips, such as N25Q128A and S25FL128. All of these flash chips use lower max frequency for instruction "Normal Read", but the datasheets don't tell the specific frequency request for different parts of instruction "Normal Read".
Best Answer
Unless the datasheet states otherwise, you should assume that the clock speed should remain consistent throughout a single command. (For instance, for a single-SPI Read Data instruction, the entire instruction should be clocked at 33 MHz; you shouldn't try to clock the instruction or address at 104 MHz.)
In any case, most microcontrollers won't even allow you to change the SPI clock speed partway through a transaction, so this is kind of a moot point. :)