Electronic – A question on sizing a blocking capacitor

My favorite electronics book is "High Speed Digital Design: A Handbook Of Black Magic". I highly recommend this book. It seems expensive, but it is totally worth the money. This book has 12 pages on choosing a bypass cap! The author, Howard Johnson, also teaches some classes with decoupling caps as one of the topics.

Some important things that I've learned over the years, and have been backed up by this book, is that the "standard practices" with decoupling caps are almost always wrong and there is more art than science when it comes to choosing and routing them.

There are lots of calculations that you can do regarding decoupling caps, but much of those are not accurate due to many things. The caps themselves are vary wildly (especially the higher dielectric caps like X7R). The PCB layout changes things greatly (and you'll need to think in 3-D for this one). Temperature and voltage will change the behavior of the caps. A single cap will behave as both a "power supply smoothing cap" and a "AC signal return bypass cap". Etc.

What Johnson did was, after a lot of experimentation, figure out that inductance is the most important factor and it swamps almost every other consideration. So the goal when selecting and placing decoupling caps is to use a lot of physically small caps, with the highest practical value, and route them so the total inductance is as low as possible.

The ideal would be to use lots of 0.1 uF caps in an 0402 package. Place them under the chip on the back side of the PCB. The cap be routed as in the image below. And the vias go directly to the power/ground planes (not to the chip's power pins, as that would usually increase the inductance). If you place the cap under the chip then sometimes you could share the same via without any issues.

The reason why a 0.1 uF cap was chosen is because it is the highest practical in an 0402 package. The reason why 0402 was chosen is because it is the smallest practical size, and you want to use a lot of them to get the effective ESL/ESR down. Of course all bets are off if you have a 2 layer PCB without power and ground planes.

I don't want to belittle the use of the math, that is important, but the complexity of power supply decoupling and AC return paths often makes the math not so practical in the real world. In the real world, a "rule of thumb" really helps. Of the many rules of thumb for this topic, it has only been Howard Johnson that has proven the other rules don't work and provided this better rule. My experimentation and experiences has shown this to be true.

All digital ICs should have decoupling caps between their power and ground pins. These should be ceramic and physically as close as possible to the IC. You want to minimize the loop length from power pin to cap to ground pin thru the IC and back to the power pin.

Decoupling caps deal with short term current spikes the IC draws. They must therefore be high frequency. Large capacitance is not necessary, and since large capacitors usually have poor high frequency response, they are worse. A 100µF electrolytic cap is pretty useless for decoupling. 1µF to 100nF ceramic is good.

As for the cap on the motor, the idea is good but I think 100nF is too large. That could cause excessive or unnecessary current to flow in the H bridge every time it switches. If you're only reversing motor direction occasionally, then this isn't a big deal. If you're using the H bridge to modulate the apparent motor drive with PWM, then you should lower the cap. Something like 1nF should still cut down the noise the motor is making while not getting in the way of switching.