Electronic – a ripple clock

clockfpgaintel-fpgatiming-analysis

I am reading Chapter 12. Recommended Design Practices from the Quartus II Handbook Version 13.1
Volume 1: Design and Synthesis which states (p. 8):

Ripple counters use cascaded registers, in which the output pin of one
register feeds the clock pin of the register in the next stage. This
cascading can cause problems because the counter creates a ripple
clock at each stage. These ripple clocks must be handled properly
during timing analysis, which can be difficult and may require you to
make complicated timing assignments in your synthesis and placement
and routing tools.

What is a ripple clock? Why is timing analysis difficult on a ripple clock?

Best Answer

In Quartus II, Ripple clock is any clock driven by the output of another register. Couple of issues with ripple clocks:

The last clock will have a delay than the input clock, because it goes through a number of flops. So what is the problem with this delay? You'll have problem when your design have cross-domain paths between these two clocks. If any path have a launching clock from the input clock domain and capturing clock coming from that derived clock domain, that path will have a large skew. So you'll have a hard time to meet the timing.
Another problem is with writing SDC constraints. You have to write the clock definitions on each stage even if they aren't used. See an example here on page 18.

Related Solutions

Electronic – ASIC timing constraints via SDC: How to correctly specify a ripple-divided clock

I'd say that the rule of thumb is: set either input port of the top module, or Q pin of an internal flip-flop as the source of generated clock.

Example Verilog code:

module top (

input clk,
input rst,

...

);

...

always @(posedge clk or negedge rst)
begin
if (rst == 1'b0) 
    div_2_clk = 1'b0;
else
    div_2_clk = ~div_2_clk;           
end

...

endmodule

Example SDC code:

create_clock -name clk -period 5 [get_port clk]
...
create_generated_clock -name slow_clk -source [get_port clk] -divide_by 2 [get_pins div_2_clk_reg/Q]

I did no test the above syntax's. Also note the extension _reg added to the RTL name of the signal - this is the extension added by synthesis tool when it detects that the signal must be represented by a flip-flop. This extension may vary between tools (I don't know for sure).

If you use any RTL wrapper around flip-flops - set the source of the generated clocks to be the internal Q pin of the flip-flop, not the output pin of the wrapper.

If you follow these simple rules you need not worry about any buffers added by the synthesis or P&R tools.

SDC Timing Constraints – How to Correctly Specify a Multiplexed Clock

Define divide by 1 clocks on the and_* nets and declare them to be physically exclusive. Cadence RTL compiler handles the situation correctly by generating 3 timing paths for registers clocked by cpu_clk (one path each for one clock). Registers directly driven by clk0, clk4 and clk_ext have their own timing arcs.

create_generated_clock -source [get_ports clk0] \
-divide_by 1 -name and_clk0    [get_pins and_cpu_1/Y]

create_generated_clock -source [get_ports clk4] \
-divide_by 1 -name and_clk4    [get_pins and_cpu_2/Y]

create_generated_clock -source [get_ports clk_ext] \
-divide_by 1 -name and_clk_ext [get_pins and_cpu_ext1/Y]

set_clock_groups \
-physically_exclusive \
-group [get_clocks and_clk0] \
-group [get_clocks and_clk4] \
-group [get_clocks and_clk_ext]

Best Answer

Related Solutions

Electronic – ASIC timing constraints via SDC: How to correctly specify a ripple-divided clock

SDC Timing Constraints – How to Correctly Specify a Multiplexed Clock

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