Electronic – Acceptable designing two clock generators using single package

The sophistication of your clock gating depends on how much the downstream logic is going to respond to a bad clock pulse.

For example: If the downstream logic is always reset after the clocks switch then you can get away with almost anything for your clock gating logic.

However, if you are expecting the downstream logic to continue functioning properly when the clocks are switched (without a reset) then you gating logic must be designed so that you never have clock pulses that are too short and violate your timing constraints.

The danger with short clock pulses that violate your timing constraints is that it could put a state machine into an invalid state that it can't recover from. This is really easy to do, so don't take it for granted that it won't happen to you.

Designing good clock gating/switching logic that doesn't produce short clock pulses is difficult and usually requires intimate knowledge of your ASIC process. Rather than invent your own, I suggest that you talk with your ASIC house or whoever you got your ASIC libraries from. Odds are very high that they already have the circuit you need.

Update:

The OP indicated that the clock gates in the schematics are from the ASIC library. If those gates are designed to not glitch (I.E., they never produce a pulse that is too short), then the only trick is to allow enough time between disabling one clock and enabling the next. In this way you can cleanly switch between clocks and not have clock glitches.

Designing the logic to do this (keep enough time between disable/enable) is still difficult, but not super difficult. On a scale of 1-10, this would be a 6. Designing a glitchless clock gate, on the other hand, would be a 10 or even 12!

is whether "fingers" A, B, D and E should be removed or perhaps they contribute to reducing crosstalk between the tracks.

They should be removed because as is they do not really help and quite possibly, will make things worse.

Your concern appear to be crosstalk. So lets talk about that for a second.

Crosstalk is when the feilds (either electric or magnetic) from one signal (trace) interact or intersect another signal (trace).

This is what a typical signals look like in the "feilds" view.

You combat crosstalk in a few ways.

1. Reduce the rise time. \$ Crosstalk \propto \frac{dv}{dt} \$ so by reducing the rise time of your signal, you are in effect reducing the dv/dt which then reduces crosstalk.

2. Move your signals farther apart. Doing this will reduce the interaction/intersection of the fields from the aggressor to the victim. The feilds are still there, but you are just tip toeing around it.

3. Bring your reference plane closer. The fields are looking are looking for their reference place. That is the path of least impedance for it. The feild lines spread out as far enough as it needs to find its low impedance path. If you bring the plane closer, its coupled much tighter.

Now if you have a 2 layer board and you cannot make the board thinner (to bring the two layers closer together), then you are left with options #1 and #2. However, you can "kind of-sort-of" implement option #3 on a 2 layer board by routing a ground trace in parallel with the signal for the entire length of the signal. The feilds are going to be there, so why not control which "signal" the fields interact with.

This is what you were trying to do with the ground pour on the top layer. In order for it to be effective, it needs to be for the entire length (or as close as possible) of the signal (basically following it like a shadow). So fingers A, B, D, E are ineffective and can possibly make things worse by being a patch antenna, but C is the only somewhat alright one, in my opinion. It's not completely effective for the signal, but it won't make things worse.