I am running DRC in Altium Designer and Im getting tons of "Silk to Solder Mask Clearence" Errors. I searched for acceptable values, but without luck. Altium is set to 10mil. I have most values around 7.5mil. Sometimes its even not possible to reduce, for example with an LQFP100 package. What would you suggest me?
Electronic – Acceptable Silk to Solder Mask Clearence
altiumpcbsilkscreensolder-mask
Best Answer
Allowed clearance between silkscreen and soldermask is usually not an issue, but when it is it's determined by the capabilities of your manufacturer. Ultimately the goal is to keep silkscreen ink off of the pads. I generally set my clearance to 0 mil but specify in the fabrication notes that there cannot be any ink on any land, and the supplier may remove conflicting silkscreen at their discretion. Specifying 0.005" (0.127mm) will probably be more than good enough. 0.010" (2.54mm) is ridiculous for a lot of boards, and can be dropped down significantly.