Electronic – Accessing RAM instance from multiple modules in Verilog

ramverilog

I am trying to make a single instance of RAM module accessible in different modules without instantiating it in every module.
Since If I instantiate RAM module in each module, there are two more copies of it, taking up twice or more as much Block RAM as needed.
There is no concern about modules trying to access it in the same time, as they run one after the other.
How can I do it?

P.S. providing memory as input to each module seems like incorrect solution..

Best Answer

If you're trying to model how actual hardware would do it, you should:

Define an interface with the necessary ports (read/write, address, write data, return data)
Add these ports to any unit which wishes to access the ram.
Create an arbitration module which connects to all the other modules with ram interface ports, and let this module arbitrate the requests of all the different modules, access the physical ram, and return the read data to the module which requested it.

If you're just doing this for simulation and you don't care about synthesis, then you can just use a hierarchical reference to a ram block somewhere (simtop.u_ram.wr_data = 0x123). But I think writing it in a synthesizable way as described above is the most clean and logical way to do it.

Related Solutions

Electronic – using ram verilog instantiation

You'll need to use the clock to break up the write and read operations. Here is an example of a test bench that writes data to two addresses then reads them back.

wire [DATA_WIDTH-1:0] data = we ? wdata : {DATA_WIDTH{1'bz}}; // tri-state write output driver
ram i_ram0(clk,we,addr,data);

initial begin
  clk   = 1'b1;
  data1 = 'h0F;
  data2 = 'hF0;
  addr1 = 0;
  addr2 = 2;
  we    = 1'b1;
  addr  = addr1;
  wdata = data1;
  @(posedge clk) #1;
  addr  = addr2;
  wdata = data2;
  @(posedge clk) #1;
  we    = 1'b0;
  addr  = addr1;
  @(posedge clk) #1;
  if(data !== data1) $display("ERROR data:%h != data1:%h @ addr:%h", data,data1,addr);
  addr  = addr2;
  @(posedge clk) #1;
  if(data !== data2) $display("ERROR data:%h != data2:%h @ addr:%h", data,data2,addr);
  @(posedge clk) #1;
  $finish;
end

FLY if data is an inout, then you need a tri-state driver in your ram module:

assign data = we ? {DATA_WIDTH{1'bz}} : rdata; // tri-state read output driver

Full working example here: http://www.edaplayground.com/s/6/221

Electronic – RAM memory modelling in Verilog

Looks like you need to rewrite the memory model to tristate the output port when cs is 0. Since this is not the case, the result is undefined as there are multiple drivers.

Best Answer

Related Solutions

Electronic – using ram verilog instantiation

Electronic – RAM memory modelling in Verilog

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