I want to convert analog output of an accelerometer to digital codes.
I understand that the sampling rate of the ADC should be with reference to Nyquist criteria.
Please let me know how to decide on the resolution needed.
Electronic – ADC resolution selection
adcanalogdatadigital-logic
Related Solutions
From page 235 of the datasheet:
Differential conversions are synchronized to the internal clock CKADC2 equal to half the ADC clock. This synchronization is done automatically by the ADC interface in such a way that the sample-and-hold occurs at a specific edge of CKADC2. A conversion initiated by the user (i.e., all single conversions, and the first free running conversion) when CKADC2 is low will take the same amount of time as a single ended conversion (13 ADC clock cycles from the next prescaled clock cycle). A conversion initiated by the user when CKADC2 is high will take 14 ADC clock cycles due to the synchronization mechanism. In free running mode, a new conversion is initiated immediately after the previous conversion completes, and since CKADC2 is high at this time, all automatically started (i.e., all but the first) free running conversions will take 14 ADC clock cycles.
This is the only paragraph where they talk about CKADC2. It's nowhere mentioned in the electrical characteristics either. Overmore, the table preceding this paragraph says 13 ADC clock cycles for single ended conversions and 13 or 14 for differential, also "conversion time (cycles)". It looks like the same ADC clock is used, and that CKADC2 is only relevant for that 14th cycle if a conversion is started when CKADC2 is high.
Yes, you would need to use the Configuration Register to activate the internal reference. You would need to perform two 16-bit writes to the device using your parallel bus.
\$\overline{HW}/SW = 1\$ (tied high)
\$\overline{PAR}/SER = 0\$ (tied low)
First
\$\overline{CS} = 0\$
\$\overline{WR} = 0\$
\$DB[15:0] = ??????????????XX\$
then
\$\overline{CS} = 0\$
\$\overline{WR} = 1\$
\$DB[15:0] = XXXXXXXXXXXXXXXX\$
then
\$\overline{CS} = 0\$
\$\overline{WR} = 0\$
\$DB[15:0] = 10?XXX??????????\$
Where X is a don't care and ? means you will need to decide what is correct based on your application.
From the datasheet:
See "Software Mode" on Page 29 and "Configuration (CONFIG) Register" on Page 31 for more information.
Best Answer
Noise is the determining factor.
You first must start with the noise level of what your Accelerometer + Amplifier puts out, lets call this N for noise. Then you need to find what your accelerometer puts out at it's maximum, we will assume that this will be some RMS value and call it S for signal.
Your SNR (signal to noise ratio) \$=\frac{S}{N}\$
The base number of Bits you need is \$ B = log_2(SNR)\$
But this is not sufficient as the ADC will have some inherent noise itself. to ensure that the ADC noise does not interfere, or to put it another way , to ensure that the ADC noise does not factor into the signal you must ensure that the resolution is greater than the B value calculated above. For a very strict definition the noise from the ADC should be 10% of the signal noise but you may find that 25% is adequate.
In your ADC data sheet you'll find a number called ENOB (Effective number of bits).
In the 10% case:
ENOB > B + \$log_2(10)\$ > B + 3.32
In the 25% case:
ENOB > B + \$log_2(4)\$ > B + 2
Next you have to scale the output of your accelerometer and buffer amplifier so that the max of is a little less than the maximum of what the ADC can handle (again from the datasheet).
If you have matched the ENOB and the scale then everything else is taken care of.