The reason your unsigned() cast doesn't work is because the result takes the exact bits in the input and just 'calls it unsigned'. ie, 0xFFFC signed is -4, but when cast to unsigned, it's 65532.
Instead, since your incoming signal is always 16 bit signed, just check to see if it is negative (as simple as checking the leading bit). Then, instead of casting to unsigned, negate it (which will have the desired effect) and then multiply by your scale factor, negating again afterwards. I can't think at the moment how to do this in a single step, but this should work for you if you can spare two extra multiplies.
Let's say that we want to do a good job of testing this, but without going through the entire 2^32 space of possible operands. (It is not possible for such adder to have such a bug that it only affects a single combination of operands, requiring an exhaustive search of the 2^32 space, so it is inefficient to test it that way.)
If the individual adders are working correctly, and the ripple propagation between them works correctly, then it is correct.
I would giver priority to some test cases which focus on stressing the carry rippling, since the adders have been individually tested.
My first test case would be adding 1 to 1111..1111 which causes a carry out of every bit. The result should be zero, with a carry out of the highest bit.
(Every test case should be tried over both commutations: A + B and B + A, by the way.)
The next set set of test cases would be adding 1 to various "lone zero" patterns like 011...111, 1011...11, 110111..111, ..., 1111110. The presence of a zero should "eat" the carry propagation correctly at that bit position, so that all bits in the result which are lower than that position are zero, and all higher bits are 1 (and, of course, there is no final carry out of the register).
Another set of test cases would add these "lone 1" power-of-two bit patterns to various other patterns: 000...1, 0000...10, 0000...100, ..., 1000..000. For instance, if this is added to the operand 1111.1111, then all bits from that bit position to the left should clear, and all the bits below that should be unaffected.
Next, a useful test case might be to add all of the 16 powers of two (the "lone 1" vectors), as well as zero, to each of the 65536 possible values of the opposite operand (and of course, commute and repeat).
Finally, I would repeat the above two "lone 1" tests with "lone 11": all bit patterns which have 11 embedded in 0's, in all possible positions. This way we are hitting the situations that each adder is combining two 1 bits and a carry, requiring it to produce 1 and carry out 1.
Best Answer
ieee.numeric_std will provide a result the length of the left operand. You could concatenate a leading sign bit or zero bit (for unsigned) with the left operand to produce your 65 bit result.
A look through the source for Synopsys' std_logic_arith shows it's "+" does the same thing.
You didn't specify signed or unsigned, this is unsigned, the operands and the results can be ether signed or unsigned instead.
This code analyzes, elaborates and simulates. It works be setting the left operand to be 65 bits long. You mentioned carry so it's shown with one in a method compatible with earlier VHDL tool implementations.
Note the "&" and "+" operators have the same priority, they will be executed in the order they are found left to right.