Electronic – adjacent trace capacitance (horizontal)

You will hate yourself if you do stack up number two ;) Maybe that's harsh but it's a going to be a PITA reworking a board with all internal signals. Don't be afraid of vias either.

Let's address some of your questions:

1.Signal layers are adjacent to ground planes.

Stop thinking about ground planes, and think more about reference planes. A signal running over a reference plane, whose voltage happens to be at VCC will still return over that reference plane. So the argument that somehow having your signal run over GND and not VCC is better is basically invalid.

2.Signal layers are tightly coupled (close) to their adjacent planes.

See number one I think the misunderstanding about only GND planes offering a return path leads to this misconception. What you want to do is keep your signals close to their reference planes, and at a constant correct impedance...

3.The ground planes can act as shields for the inner signal layers. (I think this requires stitching ??)

Yeah you could try to make a cage like this I guess, for your board you'll get better results keeping your trace to plane height as low as possible.

4.Multiple ground planes lower the ground (reference plane) impedance of the board and reduce the common-mode radiation. (don't really understand this one)

I think you've taken this to mean the more gnd planes I have the better, which is not really the case. This sounds like a broken rule of thumb to me.

My recommendation for your board based only on what you've told me is to do the following:

Signal Layer
(thin maybe 4-5mil FR4)
GND
(main FR-4 thickness, maybe 52 mil more or less depending on your final thickness)
VCC
(thin maybe 4-5mil FR4)
Signal Layer

Make sure you decouple properly.

Then if you really want to get into this go to amazon and buy either Dr Johnson's Highspeed digital design a handbook of black magic, or maybe Eric Bogatin's Signal and Power integrity Simplified. Read it love, live it :) Their websites have great information as well.

Good Luck!

Your equation:

\$ C = \frac{e_oe_rLW}{d} \$

Is the parallel plate capacitance equation and assumes that the plate size L*W is large enough and the gap size d is small enough that most of the e-field is captured between the plates. With your system, most of the capacitance will be in the field lines around the wires so the result will not be accurate.

Usually this would be simulated with software but as a first approximation you should use the capacitance of a two wire line. This will be some what inaccurate because teh conductors are a significant size wrt to the spacing. But it will be better.

\$ C = \frac{2 \pi e_r e_o L}{2 ln(2h/b)} \$

where h = 1/2 the distance between wires and b = the "radius" of the wires.

In your case the wires will not be circular (but they are not square either). but this is a good first approx..

Some open source software, that is kind of hard to use if you don't have the right tools is found by a search of "fast field solvers"