Electronic – Altera Cyclone IV memory block Verilog module

cycloneintel-fpgamemoryverilog

This document explains the various characteristics of the Altera Cyclone IV memory blocks (known as "M9K").

However, there is no mention as to how these modules should be instantiated in Verilog. Where can I find the M9K memory block Verilog module documentation? Does Altera provide example code?

Best Answer

The Recommended HDL Coding Styles gives detail on how to instantiate various memory and other functions. It also mentions other useful documents. I assume you can also use a wizard to setup memory (megafunctions I think, though you probably know this already)

Related Solutions

Electronic – Procedural blocks in verilog

Does that affect the timing of these signals?

Not really.

Yes a&b are evaluated sequentially but in the same simulator timestep, not seqential in terms of electronic design.

initial begin
  a = 1'b0;
  b = 1'b1;
end

a and b are essentially evaluated in parallel. but your simulator can not do that, the only time that this needs careful consideration is if you rely on previous results.

The following are just examples and would imply latches in some case and should not be used in RTL like this.

always @(posedge clk) begin
  a = y;
  b = a; //this is b=y
end

is not the same as:

always @(posedge clk) begin
  b = a;     //This is old y
  a = y;
end

For clocked systems (implying flip-flops) we use non-blocking (<=) the following 2 examples are the same:

always @(posedge clk) begin
  a <= y;
  b <= a; //this is old y
end

always @(posedge clk) begin
  b <= a;     //This is old y
  a <= y;
end

Simulating IP core (i.e ALT_FP_DIV) on Altera modelSim gives “z” (high impedance) as output

Sounds like you are trying to stimulate black box modules, but the synthesizer cannot find the implementation. Are you sure you have included all of the IP core components?

Best Answer

Related Solutions

Electronic – Procedural blocks in verilog

Simulating IP core (i.e ALT_FP_DIV) on Altera modelSim gives “z” (high impedance) as output

Related Topic