Electronic – Antennas- Spacing between Reflectors & Directors in Wavelengths

I got to meet Massimo at Flourish Conf in Chicago this year... and I actually asked him this same question. What is up with the odd pin spacing?! This had been a subject of debate among friends, with the general agreement being that it help you from putting shields on backwards.

Turns out, the actual reason for the odd pin spacing was an error in the original CAD/gerber file. So yea, the odd pin spacing was completely unintentional. Massimo also mentioned that there was a proposal to remove the odd pin spacing starting with the Duemilanove, Mega and future models (a so called "restart"), but was voted down in favor of reverse compatibility with old shields, etc.

Hope this helps with the odd pin spacing question.

The most cited paper on the subject that I could find is PCB design techniques for lowest-cost EMC compliance Part 1 (not free).

Though the part you're interested in is succinctly quoted in Best practice in circuit board design:

Armstrong recommends stitching at no more than λ/20, with stub lengths no longer than this. This is actually a very good rule for stitching any ground fill to the ground plane on a multi-layer design. λ is the wavelength of the highest significant frequency for the design (assume a frequency of 1 GHz if not know) where

f = C / λ

NB: C (speed of light) will be approx. 60% of free-space velocity for EM radiation propagating through a FR4 dielectric PCB.

Another technical note repeats this rule of thumb:

The common rule of thumb is to locate stitch vias no further apart than λ/10 and preferably as often as λ/20.

And gives some good reasons on why would would want to use via stitching/via fences:

There are numerous reasons to use ground via stitching on a multilayer PCB. Some of the reasons are:

• Prevention of coupling into nearby traces and metal pour.
• Prevention of waveguide signal propagation, shielding/isolation of circuit blocks, and the reduction of slot radiation from the edges of a PCB.
• Completion of a robust power distribution design. Reduction of series inductance to active and passive parts. For more detailed info on PDN (power distribution networks) in PCB, see [ 2 ].
• Signal integrity, in particular for signals that transition planes.
• Thermal reasons (not covered in this tech note).

With respect to your particular application, the WirelessUSB™ LP/LPstar Tranciever PCB Layout Guidelines state the reasoning more plainly:

The top and bottom layer copper pours provide an uninterrupted return path. This is maximized by the distribution of ground vias connecting the two layers. The internal ground plane of 4-layer designs also provide uninterrupted return path by connecting areas of copper that may otherwise be islands that do not contribute to the return path. The term “via stitching” describes the practice of placing evenly spaced vias around the board. Figure 9 shows a good distribution of ground vias with each via marked by a ‘+’. The row of more densely distributed vias along the top edge of the board is the applied antenna ground and is required to maximize the RF performance of the device.