From what I can see, the (main) difference between it and SRAM is it's slower, and the difference between it and EEPROM is it's more expensive.
I'd say it's sort of "in between" both.
Being a pretty new technology, I'd expect the price to drop a fair bit over the next year or so providing it becomes popular enough. Even though it's not as fast as SRAM, the speed is not bad at all, and should suit many applications fine - I can see a 60ns access time option on Farnell (compared with a low of 3.4ns with SRAM)
This reminds me - I ordered some Ramtron F-RAM samples quite a while back, still not got round to trying them yet...
I have never heard of a flash memory chip (or processor with internal flash) that has sufficient energy storage internally to complete a write (or erase) cycle if external power should be removed. In other words, if you don't have control over when your system powers down, you always need to create a protocol that can detect and deal with any individual flash update operation that might have been interrupted.
One way around this is to provide the necessary energy storage (e.g., an electrolytic capacitor) on your board, such that you can detect an external power failure, yet still complete any write/erase operation that may have already started.
EDIT: Your write buffer concept could be used with the external flash, but it needs to be modified to take into account the larger erase granularity. According to the datasheet, the minimum erase size is one "sector" (4K bytes).
You'll need to reserve three sectors for your write buffer. One of these will hold your READY flag (call this the WB_R wector). The second will hold the sector address of the sector being updated (call this the WB_A sector). The third will hold the updated data for that sector (call this the WB_D sector).
To update any particular byte (or a group of bytes in a single sector), follow the following steps. We assume that WB_R is already erased.
- Erase WB_A.
- Locate the flash sector that contains the byte you want to change (call this the DEST sector).
- Write the sector address of DEST to WB_A.
- Erase WB_D.
- Copy the contents of DEST to WB_D, but when you get to the byte(s) that you're changing, write the new value(s) to WB_D instead of the old value(s).
- Set the READY flag in WB_R. Note that this means you change it to its non-erased state. Since the erased state is 0xFF, this means that you write 0x00.
- Erase DEST (getting the sector address from WB_A).
- Copy the contents of WB_D to DEST.
- Erase WB_R.
On power up, check the READY flag, and if it's set (anything other than 0xFF — it may have been only partially written or partially erased), jump directly to step 7.
Note that with this algorithm, each of the write buffer sectors gets written and erased at least once for each write operation you do. This could become a problem if you do a lot (more than 100,000) of writes over the lifetime of the product. If that's the case, you'll need a more sophisticated wear-leveling algorithm.
Best Answer
The two are intended for different purposes. EEPROM (Electrically Erasable Programmed Read Only Memory) is non-volatile and used for long-term storage just as configuration parameters which might be changed by the user; results of a calculation to be read out later; and something downloaded from the Internet such as an MP3 song or e-book. You can now get a 256MB (not bit) EEPROM now for $3.
EEPROM is not suitable as a substitute (or extension of) a computer's internal RAM, since as another answer pointed out, it takes much longer to write than to read, and you can eventually wear it out.
External RAM (Random Access Memory) is like the RAM inside your computer chip, except that it is harder to access. RAM is volatile; it will lose its consent when the power goes off. This sometimes is not a problem in embedded systems, since some are designed to never be completely turned off -- the external RAM may be left powered up even if the power to the microcontroller is turned off. This is called battery-backed up RAM.
External RAM is harder to access than the RAM is you CPU because it is connected over a serial link, either SPI or I2C, since all but the highest-end microcontrollers do not have an external address or data bus. So the external RAM does not appear in the address map of you microcontroller; rather you have to access it via a subroutine to first send the address to be accessed and then the data either to be written or read back. This is way way slower than accessing the RAM inside you microcontroller.
This limitation is also inherent in accessing EEPROMs.
External RAM can be used to hold large intermediate results of a calculation, data that is being logged (here you want to use battery-backed up RAM), and material temporarily downloaded from the Internet (such as a web page, or an MP3 song you don't need to keep around).
Static RAM is at least an order of magnitude more expensive than EEPROMs of the same size. You can't used dynamic RAM (which is cheaper) without special refresh circuitry.