Verilog Nested Modules – Are They Allowed?

The code you showed has a few problems:

• You don't show how error_count is declared in the top-level module. If error_count is just declared as wire error_count;, you only have a single bit of your counter connected between the counter module and the lcd module.

• You don't show how the counter is updated in the counter module. You could have a bug there that results in the counter never updating. Since it is initialized to 0, you'd always have a 0 output from the counter module.

• You don't show any clock input to the counter module. If clock is not connected, error_counter will never be updated.

• You say that lcd has a clock input, but you don't show that it actually does, and you don't show any code where it matters.

• You don't show how your clock is generated. If there's no clock, the counter won't updated.

• You don't show the complete input and output ports to either module. With your coding style it's easy to connect a wrong input to a wrong port. I much prefer to intantiate modules with the syntax like

  counter counter1 ( .clk( clock ) , .error_count( error_count ) );

  With this style, the order of naming the in's and out's in the instantiation doesn't matter.

• You haven't shown any reset signal, but you probably have one. If the reset is stuck in the active state, probably the error_count won't ever increment.

If you want to share a parameter among a limited set of modules within your ovarall design, you can define the parameter in an enclosing module, and then pass it into the modules that need it using the following instantiation syntax:

parameter PARAM = value;

module_name #(.PARAM(PARAM)) instance_name ( ... );

Each of the lower-level modules must also declare the parameter, and they can optionally give it a default value as well (which will be overridden by the value passed in during instatiation).