I've been asked by my professor
When pipelining is better than single-cyle MIPS CPU's?
I actually answered "always", but I'm not sure that's the correct answer. Excluding an increase in design complexity, and the added complexity in handling hazards, from the point of performances doesn't pipelining always give better (or equal) results?
EDIT: I omitted I was talking about the MIPS architecture.
Best Answer
It depends on what you mean by "performance". Pipelining generally improves throughput, measured in terms of results per unit time, but it increases latency — the time that elapses from the beginning to the end of any particular computation.
Sometimes the latter is more important than the former. In particular, if the code has lots of conditional branches with only small numbers of other instructions between them, the latency associated with deciding which way each branch will go makes it impossible to keep the pipeline filled with useful instructions.
For example, suppose that converting a single-cycle implementation to a five-stage pipeline allows you to double the clock speed, but that a conditional branch requires you to flush the pipe. If 20% of the instructions are conditional branches, the pipelined implementation is already reduced to the same performance as the original implementation.
A single-cycle machine uses every clock cycle, so at 1GHz, it takes 5 ns to execute 5 instructions​.
The pipelined machine runs at 2 GHz, so it decodes the 5 instructions in 5 clock cycles, or 2.5 ns. But it takes another 5 cycles (2.5 ns) until the result of the branch is known, during which no other instructions can be issued to the pipeline. It is only after the 10th cycle that the next useful instruction can be decoded, which means that this machine also took a total of 5 ns to execute those same instructions.