Electronic – Are there any interesting present-day or historical uses of “resistor priority” logic


In many digital logic applications, it's necessary to have an output which will be derived from one signal under certain conditions, and from another signal under other conditions, etc. Sometimes the conditions may have a priority relationship.

Although it would be possible to use nested multiplexers to implement a priority relationship, a simple means of achieving such a thing is to have three-state outputs connected to a bus via differently-sized resistors. For example, for a slow-speed bus, if power dissipation wasn't a particular concern, one might have four devices on a bus–one connected with 100K resistors, one with 10K's, one with 1K's, and one with no resistors. If the device with no resistors decides to output, and is capable of sinking or sourcing 5.6mA, it will "win" rather decisively even if all other devices want to drive the other state. Otherwise, if the device with 1K resistors wants to output, it will "win". Otherwise the device with 10K's. Otherwise the device with 100K's.

To be sure, such an approach could waste massive amounts of power, especially if the 1K- and resistorless devices often want to drive opposite bus states. On the other hand, it has the advantage of being electrically very simple.

This approach is sometimes used, in a sense, with buses that have pull-ups, pull-downs, or some combination thereof to select an idle-bus condition. A somewhat nicer application exists with bus-keeper circuits, which pulls an idle bus toward whichever real is nearer. Has anyone seen or used a "deeper" multiplexing scenario, in either present-day or historical circuits? As noted, the power dissipation is nasty, but for low-speed applications it would seem that it should be possible to cascade at least four devices reliably (one probably wouldn't need a full 10:1 resistor ratio; values of 1K, 6.8K, 33K might be workable.)

Best Answer

I don't know of any examples that use the "analog" priority scheme you propose, at least beyond two levels, but the CAN bus achieves an even greater number of priority levels through how messages are transmitted. Low bits are transmitted actively, while high bits are transmitted by letting the bus return to its idle state. Each message begins with an identifier number, sent MSB first, and low identifiers have priority. As a device begins transmitting, it also monitors the bus to see if the bus state matches what it's sending. If the bit on the bus doesn't match what is being sent, then another device must simultaneously be sending a higher priority message, and transmission stops to let the high priority message through.