I'm getting a syntax error near data0_sim in the following code – New to vhdl and confused as I think this should work:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
signal data0_sim : std_logic_vector(8-1 downto 0);
data0_sim <= "00001111";
Best Answer
We can only guess since you haven't told us the syntax error, but from the code posted it MIGHT be:
Now there are two things you might be trying to do here:
1) declare a signal and give it an initial value. The correct syntax for that is:
Note that the initialiser uses the variable assignment syntax,to indicate that signal assignment semantics (postponed assignment, event generation) don't apply.
2) declare a signal and later, assign it a value.
The correct syntax for that requires more context : declarations and statements occupy two different spaces in a VHDL unit. This follows programming languages such as Ada, but it is rather different from C.
In VHDL, the context may be an entity/architecture such as: