This is my first attempt at learning Verilog HDL testbench for an AND gate:
'
'
initial
begin
//case 0
A_t <= 0; B_t <= 0;
#1 $display("F_t = %b", F_t);
//case 1
A_t <= 0; B_t <= 1;
#1 $display("F_t = %b", F_t);
//case 2
A_t <= 1; B_t <= 0;
#1 $display("F_t = %b", F_t);
// case 3
A_t <= 1; B_t <= 1;
#1 $display("F_t = %b", F_t);
end
endmodule
My question is since this is for a two input we had only four test cases, lets say we have 2000 cases, then can we use a for loop as shown below:
'
'
initial
begin
for (i=0;i<2000;i++)
{
for (j=0;j<2000;j++)
{
A_t <= i; B_t <= j;
#1 $display("F_t = %b", F_t);
}
}
end
endmodule
Is this legally correct to use loops like this? If not then please suggest me the correct method for automating the inputs.
Best Answer
'for' loops exist in verilog, but they look like this:
There is no
++
operator and you have to usebegin
andend
.It's a very reasonable way of automating the inputs. Of course you have to get the timing right, which in your case is done with that
#1
there.