Electronic – Balun/matching network question

Yes that is a legal circuit. There are an infinite number of ways one can match impedance using an infinite combination of resistors, capacitors, inductors, stub and length matching.

However, as you pointed out, the choice of passive components will create a filter of some kind. The characteristics (attenuation, bandwidth, physical size, power rating etc...) will be optimized for the application.

As an example, a version of your drawn circuit exists for high speed digital. PCIe runs at > 1GHz and terminated for 85 or 100 ohms depending on the generation. That termination is usually done inside the IC using resistive elements. However, PCB designers need to add AC coupling capacitors in series to remove DC bias between the driver and the receiver. Also inevitably the PCB adds parasitic elements. The trace running over the ground plane is one capacitive source in parallel. The challenge here is to minimize these parasitics so that they don't affect the termination much. Unfortunately board interconnects are a great source of parasitics and is actually why the termination impedance was reduced to 85 ohms in newer specifications. That fixation on impedance matching means reflections are reduced and digital signals stay within the desired logic levels. On the bright side, digital designers don't worry about filter effects (as much). Digital logic switches so fast that the filter portion isn't as important. All the frequencies are in the rise/fall time portion of the signal where reflections are prominent. Before the signal get's a chance to settle, the logic level is likely to change. The result is something called an eye diagram.

Now let's look at the analog version. An RF engineer is going to be interested in their signal across a spectrum of frequencies. Their goal isn't just to match the impedance at the center frequency, but to ensure that they have good gain (minimal attenuation) over the bandwidth. One parameter of their design is Q factor. With this filter, we can attenuate noise outside of our signal's range while preserving ours. In this case, we have a wide variety of options available and each component plays a heavy role.

Have you read the following: Atmel AT02865 RF Layout with Microstrip ? It deals with exactly what you are doing, same chip and same balun.

One of the key parameter is the FR4 dielectric thickness between the RF ground plane and the microstrips. You have listed yours as 0.18mm (7 mils). In the Atmel app note, it uses an example of 0.25mm (10 mils) FR4 dielectric thickness. So the example is a little different, but is close enough that you can apply all the considerations while adjusting for the small dimensional differences accordingly.

Since the traces are sitting on top of a ground plane, you cannot use the coplanar waveguide model for the transmission lines. Using the microstrip model and dielectric thickness of 0.18mm, I get approx 0.3mm for 50-ohm line.

Also, you do want to isolate the microstrip lines from other elements of your design. For example, a quote directly from the Atmel app note page 10 -

For microstrip designs the copper pour on layer-1 should be kept away from the transmission line. The underlying Layer-2 ground plane needs to be the dominant ground reference to minimize variables. A keep-away distance of 4x the dielectric thickness will reduce the parasitic effects of copper pour to less than 1%. In other words the gap between the microstrip transmission line and copper pour on layer-1 should be 40 mils or more.

If you look at the balanced 100-ohm connection between the SAMR21 IC and the Balun, it ends up looking more like a "T" shape dipole antenna than a transmission line. I don't think there is anyway to make that better, so just make that connection as short as possible. Also for the same consideration of the preceding quote, I would probably take away that asymmetric ground pour.

Also, I would move the antenna to the left so the tail of antenna at the right is closer to the ground plane.