TL;DR:
When using two N-FETs to implement a high-side switch should the FETs be arranged so the drains are connected together, or the sources?
Some additional facts about the current design:
1) A boost supply is being used to drive the gates above high side.
2) The gates of the two FETs are tied together.
3) The supply voltage is ~40V — bigger than the Vgs rating (+/-20V) of the FETs.
More details:
I'm working on a battery management application and need a bi-directional high-side switch to block current to/from the battery. One way to do this is by putting two FETs back-to-back, in opposite directions, as below.
edit: Note that the arrow in the diagram suggests these are PFETs. As far as I can tell, this is a typo, and should be the other way around (MAX1614 is a high side N-FET driver.)
However, opinions on the matter seem to differ as to whether the protection FETs should be arranged with sources tied together, or drains. If you look carefully at the pictures, you'll see that the FETs are arranged with drains connected together in the first, and sources tied together in the second.
As far as I can see, the first design is fine as long as the supply voltage does not exceed the Vgs specification of the FET. However, if the supply is above that, then the maximum Vgs sustained by the FET closer to the load (the left one, in both diagrams) will be the supply voltage. This will happen when the gate is driven low (i.e. to ground) whenever the gates are turned off.
Am I missing something? Is there another, more clever way to do this that I just don't know about?
Best Answer
Since the gate voltage is specified relative to the source terminal of a MOSFET, it's much simpler if you connect the sources together, and use that node as the "reference" node for the gate driver(s), as shown in your second diagram. Note that you can also tie the gates directly together if you do this.