Electronic – Breadboard 7408 2 input AND gate always supplying current, regardless of input

logic-gates

I am currently trying to wire the logic for my dual 7-segment display.

I am stuck at my AND gate, and having tried an OR gate as well I have been unable to find why, regardless of input, the output of the gate is always supplying current.

Below the inputs are shown as leading to nothing, Va is set on my DC power supply as "5V FIXED 3A."

In accordance with the diagram, the 7408 chip is being supplied the 5V in the top right and grounded on the bottom left.

Could anyone point out what mistake I am making that is causing for this AND gate to supply current regardless of the input?

Thank You!

AND Wiring

Best Answer

Yup. That's a classic, all right. One of the interesting characteristics of the 7400-series TTL logic family is that an open input behaves like a logic HIGH. It's not good practice to do this, since such unused inputs can act like antennas and start picking up noise, but it's working just fine in your case.

In your circuit, tie each input to +5 with a 1k resistor. When you want to drive that input LOW, just ground it.

And since you're just starting, you need to start developing good habits. That means do not leave any inputs on a chip floating. You can usually get away with it with TTL and LSTTL, but it will drive you crazy if you do it with CMOS. In this case, tie all 6 unused inputs of the 7408 together, and tie the whole thing to +5 with a 1k resistor.

Also, get a 0.1 uF ceramic capacitor, and connect it between pins 7 and 14. This is called a decoupling, or bypass, capacitor, and for more complicated circuits one capacitor per IC is a very, very good idea, with each capacitor connected right to the power and ground pins of its' IC. It doesn't have to be a high-voltage capacitor, since it will only have 5 volts on it.

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Electrical – AND gate output always high

schematic

^{simulate this circuit – Schematic created using CircuitLab}

Figure 1. The NAND gate is much simpler.

As you are discovering the AND gate is not so simple.

Try simulating this NAND gate and see how you get on. To make an AND gate you need to invert the NAND output. Note that in a logic chip that this would increase the propagation delay.

Note also that the I've added individual base resistors to prevent short circuiting the bases together.

From comment:

This isn't really answering my question. I was wondering about the AND gate, and also, my question is why wouldn't the output always be high? isn't the output just connected directly to +5v through R1?

No. The output in my Figure 1 is connected to a potential divider consisting of R1, Q1 and Q2. If both Q1 and Q2 turn on their resistance will be much lower than R1's and the output voltage will be pulled low - to about 2 x \$ V_{SAT} \$ = 2 x 0.2 = 0.4 V or so.

Your AND gate suffers a few problems. One major one is that using NPN transistors in that configuration you lose 0.7 V on the base-emitter junction. Anyway, as you have seen, the bias through the bottom transistor tends to raise the emitter voltage.

To have the resistance in the negative leg of your "AND" gate you would have to use PNP transistors.

schematic

^{simulate this circuit}

Truth table
In1  In2  OUT
0    0    1
1    0    1
0    1    1
1    1    0

This is still a NAND gate! You need an inverter after it to create an AND.

Electrical – AND Gate Stays Open

It would help if you had added a schematic, but from what I can see, you are missing one vital component. A pull-down resistor. What this does, is it makes sure that the inputs are at 0V when there is no voltage present at the input. Once the button is pressed, you will get your 5V and when both buttons are pressed, you get 5V at both inputs.

As it is right now, your inputs are 'floating' which means they are in a state that is unknown, which the IC could determine as a '1' state, which is why your LED is always on. This will also be why the same is true for all outputs. With these ICs, you should always tie unused inputs to GND via a pull-down resistor.

schematic

^{simulate this circuit – Schematic created using CircuitLab}

Look at the above schematic. The top one is how I see your configuration at the moment (please correct me if I am wrong). When there is no voltage applied to the input, it is left with a floating voltage and may not be at 0V.

The bottom one is how it should be. Some pull-down resistors will ensure that when there is no voltage present at the input, they will stay at 0V.

Add these resistors and you should see your problem go away.

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Electrical – AND gate output always high

Electrical – AND Gate Stays Open

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