You can't have a bridge tied load and then ground the load too.
To reduce distortion, first find out where the distortion is.
(Which stage to change first?)
And then look what others have done...
or ask a more specific question here.
Like LvW says in his answer, note that what we call Rds is not a physical resistor present in the MOSFET but it is a phenomenon which is presented by a resistor called Rds in the small signal model of the MOSFET.
You take a MOSFET, you apply DC voltages and currents to it so that it will have a certain operating point. For example, an operating point where the drain current Ids = 1 mA and Vds is 3 V. For this imaginary NFET Vt = 1 V so this NMOS is in saturation.
Now that we know the operating point of this NMOS, we can calculate values for some small signal parameters of this NMOS at this operationg point. These parameters are all derivatives For example:
$$gm = dId / dVgs$$
and
$$Rds = dVds / dId$$
Note how Rds is the derivative of Vds/Id !
The values of gm and Rds result from the physical properties of the MOSFET. So for a different MOSFET (for example, one with a longer channel) these values will be different. In general, Rds will be larger for a MOSFET with a longer channel.
But this does not explain yet why this is so.
What does explain it is the Channel length modulation effect.
For MOSFETs with very short channels the drain is (physically close to the part of the MOSFET's channel which determines the drain current when it is in saturation. As the voltage on the drain increases the depletion layer around the drain also increases in size. Worst case this depletion region can even touch the channel. This results in a low ohmic path between drain and source and Rds will be very low.
If the drain is physically further away from the source that depletion region cannot get anywhere near the channel so the channel will determine the current without the drain and it's depletion region interfering. This results in a more ideal current source behavior of the channel. For a high Rds, this is what is needed, it means dId will be very small (only small drain current variations due to changes in Vds).
Best Answer
Maybe something like this
simulate this circuit – Schematic created using CircuitLab
You have to decide if the entire amplifier (gain of 10,000) is viable.
1) Can the non-Darlington Q1/Q2 be a light enough load that Q5 (transconductor) and Q7 (stiff current source/load) will provide 100X gain?
2) can you achieve another gain of 100X in a diffpair, if the load is D1+R4
3) how to achieve negative feedback
4) how to generate a BODE plot, so you can examine the gain margin and the phase margin
5) how to compensate the entire amplifier, even if the load (not shown) happens to be a reactive (inductive, capacitive) loud speaker load of 16 ohms?
6) does the output swing around GROUND (so you need +- 12volts, or you need a large output DC_blocking cap (not shown))
7) how to bias the input?
8) is base of Q3, or of Q4, the input?
9) what is the low-end rolloff, if C2 and R9 set that highpass response?