So I'm working on a project that contains a Blackfin processor, specifically the BF592 datasheet
One thing that confuses me is how exactly the boot up process will work. During development, I plan on loading programs through the JTAG interface. This will also allow me to debug.
However when I want to actually deploy a program such that it can start up from scratch, I will need to place the program (loader file) on some type of external flash. Looking at it the BF592 datasheet, I can have the processor boot up external SPI flash.
One of the boot modes is described as follows:
SPI1 master boot from flash (BMODE = 0x2) — In this
mode, SPI1 is configured to operate in master mode and to
connect to 8-, 16-, 24-, or 32-bit addressable devices. The
processor uses the PG11/SPI1_SSEL5 to select a single SPI
EEPROM/flash device, submits a read command and successive
address bytes (0×00) until a valid 8-, 16-, 24-, or 32-
bit addressable device is detected, and begins clocking data
into the processor. Pull-up resistors are required on the
SSEL and MISO pins. By default, a value of 0×85 is written
to the SPI_BAUD register.
I'm confused. How exactly would this work? How would the SPI master know what opcode to submit to the external flash such that memory is retrieved? For example, I've been looking at this external flash IC. It requires an op code of 0x0B to be sent followed by the desired 3 byte address. How exactly would the SPI master on the Blackfin know to issue this?
I've been digging deep into the Blackfin manuals and this part just seems to be hand waved. What exactly am I missing? Is there some configuration registers in the Blackfin where this would be configured? Do I need to purchase some compatible flash IC? Is there some standard for SPI flash where the opcode 0x0B is always used when pulling data?
Thanks!
Update: I was finally able to find the dedicated hardware manual which explicitly explains the 'boot from SPI' sequence. See page 690. This says that it issues a 0x03 or/and 0x0B opcode.
Best Answer
Yes, the Blackfin "just knows" that it needs to issue a read command followed by an address (all zeros) in order load software from external SPI flash. Devices from different manufacturers (mostly) use the same set of commands.
The code that does this is stored in a small ROM inside the Blackfin chip itself. You have to dig for it, but Analog Devices usually has the source code for that ROM hidden away somewhere in the library files that come with the software development tools, in case you want to look at it.
I have had occasionally needed to work around bugs in the ROM bootloader with respect to specific SPI flash devices by creating an extra stage of bootloading for my project. I use the ROM bootloader to load a second-stage bootloader from the SPI flash, which then loads the application code. The second-stage loader is mostly a copy of the ROM bootloader, but it is constructed to live within the limitations of the ROM code, while also fixing the bug related to getting the application code loaded.
If you're interested in the gory details, I wrote a Circuit Cellar article about it. The article itself is not available online, but the associated archive contains the source code for my replacement bootloader, and the comments there explain exactly what the problem was.