Electronic – Can CML differential signal lines be flipped to act as a NOT gate

The naming scheme on the primitives in your image suggests that this design is intended to be implemented in an FPGA.

If this is the case, gating a clock network is not recommended. Clocked logic elements in an FPGA can usually only be clocked by dedicated clock networks. These networks are only available in very limited numbers (i.e, perhaps a dozen on the entire chip!). Instantiating logic which passes a signal from combinational logic to a clock will typically result in one of these networks being used for that signal, making it unavailable for other logic on the chip.

To avoid this, most FPGAs will make logic primitives available with separate combinational logic "enable" signals. (Xilinx calls theirs FDCE/FDPE/FDRE/FDSE depending on the state at reset, and Altera calls theirs DFFE.) These logic elements will (more or less) AND the clock signal with the combinational enable signal, giving the same result as your schematic here without the detrimental effects on clock networks.

My question is, why should we try to impedance match a differential pair connecting CML devices? Does differential impedance even mean anything since the conductors will never carry equal and opposite signals?

You have to dislocate the DC scenario from the superimposed AC signalling. Numerically the current may not reverse but, as far as sending data down a balanced pair of wires you need a balanced load.

Would it not be better to treat each conductor individually and match them to the single ended impedance of the devices?

However, twisted pair is a tad notorious because it tends to require a balanced load that is not only transverse but longitudanal as well so, your 2nd quote does carry a certain amount of decent weight of truth.

In my experience with +100Mbps data signalling I've tended to fall towards treating a piece of twisted pair as two individual wires and used 2 balanced load impedances connected to screen.