Electronic – causing this level shift in the wave

h-bridgemosfetringing

Excuse the quality, sorry;

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RED is GATE of Q2.
YELLOW is GATE of Q4.

5V INPUT AT ALL STAGES

What are possible reasons that my H-bridge has a little 'bump' at the turn-off of the high-side?

It's reflected on the Vin(bridge) too;

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Circuit:
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(also here )

I've added a new shiny ceramic capacitor to the Vbridge and GND connection, but no dice. Could it be that having a ground common to my H-bridge ground is bad?
Or perhaps the capacitor is refusing to discharge beneath 6V~ for a more obscure reason?

EDIT: It's driving a 15-20mH load, but the bump is present with no-load and resistive loads on the order of 1000R, 100R, 10R.

EDIT2: Also, I've noticed that if I put in above 17V to the bridge, the power supply I'm using just shuts itself down and I have to restart the circuit.

EDIT3: Here's a bunch of images of measurements I made.


Q2 DRAIN to GND

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Q2 SOURCE to GND

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Q1 SOURCE to GND

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Q1 and Q2 GATE to GND (10V)

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NEW WAVES

5V H-BRIDGE OUTPUT

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10V OUTPUT

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Q2 Gate/12V

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Best Answer

It's fairly straightforward. When Q2 is turned off, Q4 is already off. As a result, the output, LVCoilA, is left at an intermediate voltage. This is probably determined by a combination of the two MOSFETs' off current, combined with the capacitances of each MOSFET, producing a sort of voltage divider. If you look simultaneously at Q2 gate and LVCoilA, you'll see that the gate is set to the bootstrap driver's reference, which is LVCoilA, about 6 volts in this case. Since LVColA is also Q2's source, Q2 is turned off.

When Q4 is turned on, you'll see LVCoilA, as well as Q2's gate, get pulled down to ground.

As for the noise on the voltage bus, in order to make much sense of it, you must simultaneously display (for instance) Q2's gate and +12. As it stands, the two traces differ by x5 on the timebase, and there is no obvious way to be sure which +12 transients occur with which gate events.