ceramic should work as long as you meet the requirements in the datasheet: 0.1ohm < esr < 5ohm and srf > 1mhz.
Its probably easier to find those properties in a tantalum cap, especially back in 2002 when that datasheet was released.
EDIT: Some more info about LDO stability and why the ESR has to fall in a particular range.
A generic LDO works by comparing the output voltage to an internal voltage reference with an error amplifier and driving a PNP transistor to correct for this error.
The problem comes in when you look at the phase shift and loop gain of this feedback path. The error amplifier and the load being driven both contribute poles to the frequency response of the feedback loop. These poles act as a low pass filter resulting in loop gain decreasing as frequency increases. As we know a pole also introduces a negative phase shift. If this phase shift is allowed to reach -180deg the feedback loop becomes unstable and the LDO will oscillate.
What this means is that every time the error amp tries to compensate for an error the result of its correction is 180deg out of phase, or inverted, consequently the error amp is basically thrown for a loop and begins making the opposite correction that it should be making, resulting in wild instability.
To avoid this situation we need to prevent the phase shift in the feedback loop from ever getting to -180deg, actually we only need to keep it from reaching -180deg within the region that the LDO can generate gain > 1 as the damped response of the system past this point will prevent oscillation. This frequency is defined by the unity-gain point of PNP pass transistor.
The way we prevent this phase shift is by using a capacitor with a ESR in a certain region. The capacitance will shift the pole created by the load but more importantly the ESR will contribute a higher frequency zero. Basically you've added a high pass filter to the feedback loop. The phase shift introduced by the ESR will work to counteract the phase shift introduced at lower frequencies by the poles from the error amp and the load.
The reason that the ESR has to be in a particular range is that if its too low, the zero contributed to the frequency response will be located very high in frequency, above the unity-gain point of the pass transistor. As a result its not effective in making sure the phase shift of the feedback loop doesn't reach -180deg before the unity-gain frequency.
If the ESR is too high, the zero will be very low in frequency. There is another pole in the frequency response created by the parasitics of the pass transistor, if the zero from the capacitor ESR is too low in frequency, this pole will be reached while we still have gain > 1, this will cancel out the effect of the ESR zero and we will likely reach -180deg phase shift before we reach unity gain.
All that said, these problems are indicative of older LDO designs. Many/Most/All new designs include additional internal compensation in the feedback loop which uncouples LDO stability from the ESR specification of the output capacitors.
Most ceramic capacitor dielectrics show piezo-electric effect, which causes them to vibrate with the applied voltage. If that voltage has an audio frequency the vibrations may be audible.
That's no reason for concern, hundreds of billions ceramic capacitors are produced each year which show this effect, and which perform fine on the PCB.
The sound can be reduced by using smaller packages. In larger packages stretching/shrinking the PCB may act as a soundboard. With smaller packages this effect is smaller.
Note that there are no measurable piezoelectric effects in Class 1 capacitors, such as C0G or NP0 - neither of which is considered ferroelectric.
Further reading
Piezoelectric effect in ceramic chip capacitors
Best Answer
The microphonic bandwidth is not decoupled from the electrical bandwidth of the capacitor. The piezoelectric effect will cause strain in response to an electric field, or generate an electric field in response to strain. If you can use the capacitor at that frequency, then it is vibrating at that frequency, and will happily generate voltage noise if vibrated at those frequencies. In fact, it will generate noise for itself due to local mechanical ringing.
In other words, there is no free lunch. The microphonic bandwidth can be assumed to be close to the AC bandwidth of the capacitor. If you're sampling at 200kHz, and expect a few ppm (a few µV) or less of noise, then, to put it bluntly, you cannot use an X5R or X7R ceramic capacitor.
Note, many film capacitors will also exhibit a degree of microphonics due to having a soft, flexible dielectric and vibration causing compression waves through the plates. But they generally will be much lower - but still possibly in the microvolt range.
I am curious why you have seemingly already ruled out the best candidate, a nice little 10µF tantalum capacitor. Sure, there are doubtless people groaning about their high leakage current right now, but that is silly. Who cares? You're storing charge for 5µs.
The first hit for low leakage tantalums yields this datasheet for a nice line of capacitors by Kemet. A quick scan shows me they have a 10µF Tantalum capacitor with 800mΩ ESR and DC leakage of 1.5µA. That translates into a voltage change of 160nV over 5µs. In other words, who the hell cares? If you can tolerate higher ESR, there is one that will change only 80nV. And there are plenty of other tantalums that have much lower ESR but also have leakage that would place you below a 1µV of change for 5µs.
The thing is, tantalums are naturally very low noise, and based on the information you've given, I would think they would be the ideal choice for a sample and hold application considering how very brief the 'hold' time is in your circuit.
If you still can't use tantalums for whatever reason, then I strongly recommend Polyphenylene sulfide film capacitors, as these have voltage noise almost as low as C0G. Unfortunately, a 10µF PPS capacitor will be very chub indeed, the ones on mouser look to be $15. But no one said precision was cheap!