Google has announced a contest to design a kW-scale (>2 kVA loads) power inverter with 90% size reduction compared to present designs. The goal is running household appliances from a small inverter, which somehow encourages more usage of solar power. (It would also be useful in their data centers.)
What are some challenges in such a design? In laptop wall adapters, the power density has been dramatically increased over time by moving towards higher-frequency switching regulators, which permit use of smaller components. Also better 3D modeling to permit packing components more tightly into the space.
Are such techniques likely to improve inverters as well, or would they present different issues to overcome? What approaches are likely to be taken? They are directly encouraging use of gallium nitride (GaN) and silicon carbide (SiC) components. Is it likely that custom silicon or other components would be necessary, or is it plausible such a design could be built largely with off-the-shelf components?
Best Answer
The 'little box challenge' lower power density target of 50 W per cubic inch translates to just over 3 kW per litre, which is a more widely-used unit in the literature.
For a 3-phase DC-fed inverter for a motor drive application, in which there is very little energy storage requirement, 30 kW/litre, i.e. an order of magnitude beyond the 'little box' targed, has been demonstrated:
https://www.semiconportal.com/en/archive/news/main-news/110906-nedo-sic-fupet-inverter.html
To achieve the required low input current ripple (which equates to a low input power ripple) whilst supplying single-phase AC output power with its inherently pulsating nature, energy storage within the inverter is required (in other words, 1+1 = 2).
A good example of what can be achieved may be found in the following paper (2.75-4.86 kW/l, 94.9% peak eff., all-Si):
http://itohserver01.nagaokaut.ac.jp/itohlab/paper/2013/ecce_us/ohnuma.pdf
(Not all the efficiency figures match up and there's no photo of experimental hardware, but it's an example of something in the 'close, but no cigar' range for the LBC). There are a number of publications on this technique or variations thereof, allowing greater capacitor utilisation than the conventional 'bulk' DC link filtering approach, which results in a significant 'DC' energy storage overhead if low voltage ripple is required.
As evidenced by the 'Pareto Front' diagrams (see also detailed work by Kolar et al. of ETH Zurich), extreme efficiency and high power density don't necessarily go hand in hand, and whilst you can get some way by throwing more silicon (or SiC) at the problem, self-discharge and gate driving losses place an upper limit on this. See Infineon's CoolMOS C7 application note ('Mastering the Art of Quickness') for examples.
There are several trade-offs to be considered here - the increased losses (and therefore heatsink volume) of a higher switching frequency vs. reduced filter component dimensions, for example. All well-understood stuff. I'd suggest that the 'clever' is in simultaneously optimising the various design trade-offs and maximising the performance of the individual components.
The factor that's not an issue here is cost (or reliability, beyond a 100-hour test). On a 3-dimensional plot of cost per kW vs. efficiency vs. power density, I'd hazard a guess that a typical small commercial solar inverter is as far up the efficiency curve as possible for a strict cost limit, sacrificing power density in the process.