I'm trying to pick a crystal and load capacitor combination for the atmel UC3C series micro controller. The target CPU clock I'm shooting for is close to the max frequency of 66 MHz.

Here's the configuration I think would best achieve this goal:

A `11MHz`

crystal is attached between XIN0/XOUT0 with the appropriate load capacitors. Then use the PLL to multiply the frequency by `6`

. Use the PLL `66MHz`

as the cpu clock with no division.

Now here's where I have a few questions:

I've spec'd out a variety of 11MHz crystals. All of them have 50ppm frequency stability and 30ppm frequency tolerance. However, there are various ESR. According to this source the ESR represents roughly the bulk losses in the crystal so a lower ESR value would be the better choice. Correct?

Is there a significant difference between how I arrive at the CPU clock 66HMz frequency?

I have a few choices in addition to my original choice of a PLL multiplier of 6:

- Multiply
`11MHz`

by`12`

, then divide by`2`

for a PLL output of`66MHz`

. No CPU clock divider. - Multiply
`11MHz`

by`24`

(`multiplier = 12`

,`divider = 0`

). CPU clock divider of`4`

. - Multiply
`11MHz`

by`12`

,`PLL divider = 1`

for`132MHz PLL output`

. Use a CPU clock divider of`2`

.

All of these appear to be equally valid minus the level of code complexity to achieve each choice. Should I stick with my current "simplest is best" assumption, or do one of these other solutions create a better cpu clock?

All of the crystal I've found at `11MHz`

require either a load capacitance of `18pF`

or are in `series`

. Is there any reason to choose one over the other? I can't tell anything different between the specs (same frequency tolerance/stability, same ESR, roughly same temperature range) Atmel's documentation only shows parallel crystal configurations.

If I do end up using a parallel configuration, how close should the load capacitors be to the specified load capacitance of the crystal?

Atmel's datasheet provides an equation for calculating the value of each load capacitor:

$$

C_{LEXT} = 2(C_L – C_i) – C_{PCB}

$$

`C_i`

is provided in the datasheet as `1.7pF`

. I'm unsure how to calculate `C_{PCB}`

, but I would imagine it is greater than 0. This means that `C_LEXT`

is at most `32.6pF`

. There are some `30pF`

, `32pF`

, and `33pF`

`1% C0G`

capacitors. I would think that the `30pF`

capacitors are the best choice because they are still relatively cheap compared to the `32pF`

capacitors, and don't exceed the `32.6pF`

limit as the cheapest `33pF`

capacitors. Am I right in my assumptions and conclusions?

Finally, is this a good setup? Are there other frequency crystals I should consider researching?

## Best Answer

My seat-of-the-pants understanding for load capacitors (corrections invited) goes like this:

When a crystal is cut for a certain load capacitance, it is measured with that capacitance across it during final factory trimming. There is nothing magical about the value. It is simply a way of saying, that if you design your circuit to present that same capacitance, then your crystal will be within the stated (.005% or whatever) tolerance.

So, you add up all the capacitance in your circuit, and then add in what's needed to bring it up to the spec. We'll use your numbers. The stray capacitance due to the traces on the board obviously will vary with the board, so let's guess 1.3 pf. A number I made up, to go with the capacitance of the microprocessor's oscillator, stated to be 1.7 pf. So, we've got 3 pf in parallel with the crystal. The crystal wants 18pf, so we have to make up the 15 pf difference with discrete parts.

Since the two load capacitors are in series (Gnd->cap->xtal->cap->Gnd), we double the cap value to 30pf. Two 30 pf caps in series give us the 15 pf we're looking for.

Note 1. I tried searching for typical PCB stray capacitance. It was all over the map. Suffice it to say, that as the hardware gets smaller, the capacitance will keep getting smaller. A lot of typical values claimed less than 1 pf.

Note 2. If there is more capacitance than spec, the crystal will oscillate at a lower frequency than specified. If there's less, then it's higher. You can see, that if you want to trim the oscillator to spec, it's easier to shoot for a lower capacitance and add some later, than to try the opposite.

Note 3. For fun, look up "gimmick capacitor".

Note 4. My "seat of the pants" explanation is sufficient as an introduction, and this technique works in many cases, but not everywhere. For a more in-depth look at the EE principles behind those capacitors, see this answer.