I would modify your approach a bit.
simulate this circuit – Schematic created using CircuitLab
(N.B. The values given are exact. They can be substituted for standard values in exchange or performance, or multiple components put in series/parallel to get the exact values.)
Add the gain stage first. The amplifier has an AC gain of a bit less than 11, but 1 at DC. This will maintain your DC offset for the ADC without it getting amplified. R1 and C1 still form a high pass filter, which is why the AC gain decreased slightly. AC gain can be added my increasing R2.
The second stage is an active second order low pass filter implemented using the Sallen-Key topology. Corner frequency is determined by \$\dfrac{1}{2\pi RC}\$ where \$R=R_3=R_4\$ and \$C=C_2=C_3\$. I think you'll benefit from the more aggressive roll off of the second order filter vs. the first.
In power-plane-layer-less designs you should prefer the power for higher-power devices to route separately from the power to lower-power devices and take care of return-paths as much as possible.
That means, if you have cause for worry, route the LED power and its return ground along the same path to avoid interference.
I have to agree with Laszlo though, that in a digital-domain only schematic a few millivolts are not going to give you much grief.
But if you still want to improve the noise immunity you may want to place an extra 10uF or 22uF or something in that range depending on the amount of "ick" your supply might introduce at a load next to the pins that power the LCD, just to take the edge off.
Further you should connect the decoupling capacitances (82nF ~ 330nF, depending on your own transient current requirements) as directly to the pins of your digital devices as possible.
If you then still have worries, a few uH in the path to the uC along with an extra 10uF ceramic will help a lot, but beware that this has serious implications if the uC starts switching things with several mA transient going out of its I/O pins. You stand the risk of effectively increasing what you notice of your own on/off outputs, so you should save this to the very last if you have proven in a test set-up to be bothered by incoming noise more than you expect to cause yourself. (Or have been able to simulate/calculate the effects and weighed them or can use those results to adjust the component values for correct poles/zeroes, etc.)
As for your Crystal Layout, it seems okay to me. I wouldn't be too worried about rip-up and retry, as the ring can function as a reminder to allow for isolation.
One thing you might want to think of if you want exceptionally high accuracy is that the uC's pins and your PCB introduce a certain amount of capacitance (between 0.1pF and 4pF are known values) and that you want your PCB tool to make a prediction, or that you might want to measure those, to adjust the capacitors, as the crystal's accuracy is measured at exactly the right capacitance.
EDIT to answer your later questions:
You are correct in your assumption that the differentiation between the large and small capacitors is due to transient speed. Usually you prefer small caps, for size considerations, so a 1uF 0805 capacitor would have a higher ESR than a 100nF 0805 type, but a 1uF with similar ESR as the 100nF type would be at least two to three times as large as the two capacitors together. Not to mention that standard 0805 caps are much cheaper.
As far as the display goes, probably a single 1uF or 220nF 1206 type or similar size should give you the limit of usefulness. Flooding the design with capacitors is not necessary. Also consider that if the display is made properly that all of its chips will have decoupling as well.
The capacitor close to U4: I am assuming your write-protect trace from U4 to the pin header can be a little longer than it is now, as the jumper will be purely DC during operation. So just route that wire on the outside and lay the capacitor directly between the VCC and GND traces, no fiddly business with Via's needed and a better return path for your U4.
Probably it would not make that much of a difference for the levels of "speed" you are thinking about, but as a general design rule every few mm of trace you shorten between the chip and decoupling is going to increase high-speed performance of your digital components and transient/swing performance of your op-amps.
Best Answer
The simplest thing to do to start with is to add some smoothing caps on the 5V line - a 10uF ceramic and something like a 47uF tantalum would help to keep some of the lower frequency ripple under control.
If you can adjust the voltage of your DC-DC, one option would be to increase the voltage to say 5.3V, and then use a low noise 5V LDO (e.g. TPS7A85) which will help to clean up any switching noise. Setting the DC-DC voltage to just greater than the drop-out voltage of the LDO will help to keep losses and heat generation to a minimum.
Additionally you can look at splitting your supply regions up using feed-through capacitors. These act like L-C filters and have great noise rejection. By placing one between the main power supply rail and sensitive components, you can isolate some of the noise in the system.
Finally for sensitive components, you can add more than one ceramic cap close to the power pins. If you use a series of values in parallel, such as 0.1uF + 10nF + 1nF, with the smallest value closest to the power pins, you will increase the effectiveness of the filtering over a larger range of frequencies.
As an example, we are working on a 12-channel 370MSPS ADC board with ultra low jitter clocks. As it stands that board has 12 amplifiers, 6 ADC ICs and a clock generator. Each one has local power planes, separated from the main power planes using feed-through capacitors to isolate noise. We have ended up with 43 power regions, supplied by 12 LDOs which are in turn supplied by 7 DC-DC regulators. On that board there are over 600 capacitors alone!
The one thing we have done on this board is to not split up the ground planes. There is a nice application note (I'll see if I can find the link) which explains how actually splitting up the ground plane can cause more issues than it solves from a noise perspective. The key thing is to keep an eye on the placement of components - for example keeping noisy things like switching regulators away from sensitive analogue circuitry. By keeping an eye on when the current return paths will be, you can keep noise contained even on one single ground plane.