clearanceisolationpower supplysafety
It is a snapshot from an AC/DC converter. do I need to consider "dist. 1" or "dist. 2 at" the below image to measure the correct clearance space.The caps are both Electrolytic that have an aluminum body.
If I need to refer the dist. 2, isn't there an issue on the below reference design on the marked part?
KiCad (version 5) works on a maximum required clearance model. That means that it will select the smallest clearance possible from the combination of requirements. In your case, although your pad has small enough clearance, I suspect that your zone fill has a higher clearance set.
In the image below, you'll need to set two things: the clearance and the minimum width. Because you want the copper to flow between the pads, you'll need the width to be smaller than the space available between pads (when including their clearance.
You said that you don't want this to affect other things on the board. In that case, you can set the minimum clearance for other elements using the "Design Rules -> Net Class Editor" clearance setting. Then, as long as your other footprints are set to a clearance of "0" (and their pads are set to "0"), it will use the netclass value.
Viewing the Soldermask
To view the soldermask, you need to have the soldermask layer enabled (and probably selected). The check-mark enables it but because it is drawn behind the pads, they typically obscure the layer unless you also click on it to make it the front-most layer drawn.
You can define several footprints for the same opto IC. Define a HV-Footprint which includes the slot in the footprint.
Then modify the DRC and exclude the opto IC from the clearance 8mm. Due to the slot in the footprint this should be OK, as you cannot forget it.
I would do it this way:
name: "ClassName" and value: "exclude_8mm_clearance" to every IC you want to exclude. This will add this devices to the component class "exclude_8mm_clearance"
Best Answer
The can of the capacitor should only be assumed to have functional insulation between itself and its pins. Therefore in this case the clearance should be between the bounding surfaces of the electrolytic capacitors on both sides. That could be dist2, although @Misunderstood pointed out that that marks the silkscreen, not necessarily the outside of the cap.
In your first picture it actually looks like there is less clearance between the top of that same capacitor and the copper adjacent to it. I would think that would be the shortest distance and therefore the clearance.
As for your second question, the amount of clearance required depends on a few factors which are not clear based on what is known about the circuit. For example, mains transient voltage, and the pollution degree of the board. See also Section 2.10.3.3 of IEC 60950-1.