Can An Operational Amplifier Circuit Be Made Entirely Out Of Diode Nand And Nor Gates?
This apparently simple-enough question is somewhat ambiguous and can be answered several ways.
Spehro has assumed that you convert the input to a digital value and perform digital arithmetic on it. So he says the answer is yes.
ScottMcP takes your question at face value, notes that you say "diode gates", which have no gain, assumes that you want to use the digital gate as an analog amplifier, and as diode gates have analog gains of < unity, says no.
WhatRoughBeast also takes the "digital gate as analog amplifier" and notes that the digital gate lacks features needed to make an opamp. But he also notes that you can make a single input amplifier using a digital gate as an analog gain stage.
- Placeholder adopts "digital gate as analog stage" approach BUT goes the second mile and shows how a "true" [tm] differential input amplifier could be constructed.
There another option, not covered so far. That is, inputting analog signal into a digital gate which is acting as a "digital" oscillator (albeit using an analog timing delay) so that the gate outputs a digital signal, but the gate's digital operation (in this case the oscillator mark-space ratio) is affected by the analog signal, allowing amplification in the digital domain and then conversion back to audio.
Below I cover the "digital gate converted to an analog amplifier" aspects and then introduce the rarely seen [draws deep breath] "digital gate acting as an analog amplifier while producing digital output which can be easily be converted back to analog" concept. Usually more fun than useful, but potentially of value 'in an extreme situation'.
So:
Gate is digital, signals are analog"
No, not if the gates are used as digital logic gates and the amplifier deals only with analog signals.
Diode resistor logic gates with no gain.
And, also no, if the gates have no "gain".
- Diode & resistor only gates have no gain - but they are also never used in anything practical because of loading by subsequent stages.
"DTL" gates operating in analog mode.
Only "sort of".
DTL = Diode-Transistor-Logic gates can have gain and can be made into (not very good) amplifiers by using them "strangely". The series diode connected inputs place constraints on what can be achieved with analog inputs. You'd have to be very keen.
More modern digital gates in analog mode:
If you are prepared to use digital gates in analog mode, as is done in some applications, then yes, it can be done. This is relatively unusual in everyday use and is usually a compromise or "done for fun" or extreme cost cutting.
General background:
An "Op-Amp"is an analog signal amplifier with high gain (Vout/Vin = "high", a high input impedance and a low output impedance. I could explain what "analog" means in this context but, if that's unclear, it's an essential part to understanding the question, let alone the answer, and you can very easily research it yourself.
If SOME digital gates have connections made from output to input via a resistor or resistor network, they can be biased into a linear state and then used as an analog amplifier.
Some Diode AND and OR gates MAY be able to be biased in this manner and so used as an amplifier. This is not using them in their intended mode and the amplifier quality would be poor. The diodes would add very significant distortion. Even older RTL logic may work better than this but it's still not a true digital gate when used this way.
Example of a modern CMOS gate being used in an analog biased mode to create a lineara amplifier.
Circuit is from here
They say:
CMOS inverters can be used as linear amplifiers where negative feedback is applied. Best linearity is achieved with feedback applied around three inverters which gives almost perfect linearity up to a dynamic output of 5 V peak to peak with a 10 V supply rail The gain is set by the ratio of Rl and R2 and the values are typical for a gain of 100. The high frequency response with the values given is almost flat to 20 kHz. The frequency response is determined by Cl and C2..
This circuit is not suitable for low level signals because the signal to noise ratio is only approx 50 dB to 5 V output with the typical values shown.
Analog amplifier with purely digital gate:
You will only rarely find this concept described. It works.
BUT (and many people are not aware of this) you can use some sorts of digital gates as analog amplifiers while remaining in a digital mode. This is a rather (or very) special case.
eg if a 74C14 Schmitt triggered input inverter has a resistor connected from output to input it will oscillate (for a certain range of resistors), using stray capacitance as part of the RC timing circuit. If you now AC couple an AC signal to the input the output will be pulse width modulated. If you low pass filter the output signal you can get amplified analog. Ask me how I know :-). The secret to "keeping it digital" is the Schmitt trigger input. The gate cannot be biased into a linear mode due to hysteresis and oscillates instead.
fosc should be >> finput. As the gate input is driven above half way by the incoming AC the negative to positive transition times of the oscillation are skewed, and similarly as Von falls below half voltage, but with opposite effect on mark space. The resultant output is variable mark-space PWM driven by Vin. Filtering this AC signal recovers the amplified signal.
Diagram based on this original
Best Answer
Since I just explained this to my daughters.
The bottom transistor is an NMOS transistor (an N-channel CMOS transistor). It works as a voltage-controlled switch. If the gate (the middle pin) is high (> 1V or so), it acts as if you pressed a push-button. It is ON. Otherwise, it is OFF.
The upper transistor is a PMOS transistor. It works in the opposite way. It is OFF when the gate is HIGH, and ON otherwise.
For the lower logic, the output is connected to ground when the NMOS is ON. It is ON when NOR(d, NOT(e)) = !(d + !e) = !d !!e = !d e = AND(NOT(d), e). I.e., the output is LOW (connected to ground) when the data is LOW and enable is HIGH.
For the upper logic, the output is connected to VDD (HIGH) when the PMOS is ON. It's ON when the gate is LOW. The input is NAND(d, e) = !(de). So, it is ON when both data is HIGH and enable is HIGH.
So, as far as I can see:
Notice the Z output. When the enable-pin is low, the output pin is not connected to anything, i.e. it is floating.