A chip I'm working with (SA612 mixer) has an internal BJT, and it requires the user to add discrete components to make an oscillator of a certain frequency to drive it. It gives generic Hartley and Colpitts layouts as examples:
Relavent part of SA612 internals:
The Hartley layout seems pretty easy to understand: C1 and L1 form the tank, and C2 and C3 are coupling caps. But the Colpitts layout doesn't look very much like the traditional Colpitts oscillators I'm used to, and I'm struggling to understand the role of each component.
Best guess: Perhaps C4 is a coupling cap, and the other three caps make up the capacitive half of the tank in the arrangement (C3 + C1)||C2 ? But then why do we have the parallel C2? Is it just for fine-tuning like some kind of dual of the Pierce configuration?
Thanks!
Best Answer
Data sheet suggests that local oscillator injection amplitude should be limited to something like 200mV - 300mV peak-to-peak amplitude at pin 6. If you treat C4 as a low-impedance coupling capacitor, chances are that oscillations will start easily, but amplitude will build to be too large (a).
You can increase capacitive reactance of C4 to make a less-aggressive oscillator having lower amplitude. To keep the same oscillator frequency, C2 is added (b).
These examples illustrate an oscillator around 20MHz. using a coil Q of about 200. This may be a bit optimistic...you may risk non-oscillation in (b). In any case, you can adjust amplitude with C4.
simulate this circuit – Schematic created using CircuitLab
Edit:
Example (b) is likely a feeble oscillator, whose amplitude (if it oscillates at all) is lower than 200mV p-p. Better to make it more robust than necessary than risk no oscillation. Do this by increasing value of C4.
Many circuits take advantage of the very low DC voltage between collector and base to limit oscillator amplitude...the base-to-collector junction becomes forward-biased on positive-going peaks of the oscillating wave. Doing this reduces the loaded Q of the oscillator, which adds phase noise, and decreases frequency stability as well.
C3 & C1 (both 100pf here) are greatly affected by transistor AC currents, which are non-linear. So treating them as simply 50pf from base-to-ground is a gross approximation. But its a starting point.
When you employ in cct (b): C2 > C4, the "tank" reactance of C2 combined with parallel L1 is a reasonably accurate, linear calculation. A small value of C4 makes the tank reactance dominant over the transistor-affected squirrelly reactances of C3, C1. You can almost view a 10pf C4 as being in parallel with the tank capacitance (C2 of 50pf). This calculation would yield a frequency on the low side.