Dropping 5 to 3.3 V at 250 mA will mean having to lose 0.425 Watt in the LDO, you will need a massive heat sink to make that work.
An LDO will never be more efficient than a buck converter, unless you need so little current that the power used by the regulator itself becomes an issue.
I have a mis-designed PCB right now where I tried doing exactly what you are proposing to turn 5 V into 3.3V at 200 mA and even though I have a large'ish copper plane as a heatsink the LDO still reaches 80 deg C in a few seconds.
I'm currently redesigning my power supply to use a MC34063A converter in stead.
Tying multiple LDO's together is a bad idea. No two are going to have exactly the same output voltage regulation point. One will take more of the load than the other, possibly stressing it more than it should be.
No, you can't assume you know the temperature response of a regulator only because you think you know something about the temperature response of its final pass element. There is a whole feedback and control circuit in there, quite likely with temperature compensation. Unless the datasheet explicitly tells you, you can't make any assumptions about the output voltage regulation point as a function of regulator temperature.
Some regulators have internal thermal shutdown which will prevent damage due to over current, but that's not going to be good for maintaining the output voltage. When one shuts down, the others have to pick up the slack. If you're lucky, the first one will come back on before the rest shut down, but that's hard to guarantee. Even if enough always do stay on, the output supply will likely be glitched at the on/off transitions.
Even if the regulators have enough softness in their output voltages so that others will share the current, it's still not a good idea because each has its own controller, and those controllers will be fighting. You could quite possible get oscillation of the output voltage.
The simplest way to make multiple regulators share current is to put a small resistance in series with each. For example, separate 100 mΩ after each regulator, then the outputs of those tied together might work. Make sure each regulator has its own output cap, which must be immediately at the regulator before the resistor. The downside of this is that the DC resistance of the final supply will be higher than before. Whether that's OK or not is up to you to decide. If you tie 4 regulators together, each with their own 100 mΩ resistor, then together they only add 25 mΩ to the impedance of the regulated line. That would be good enough in many cases.
Depending on how low your headroom voltage really is, this standard trick for making a high current regulator from a low current one might work:
This adds the B-E drop of the transistor to the headroom requirement of the regulator.
As the current thru the regulator increases, the voltage on R1 increases proportionally. Eventually the voltage on R1 gets high enough to turn on Q1, which then starts shunting current around the regulator directly from the input to the output. The maximum current thru the regulator will be the B-E drop of Q1 divided by R1, which should be about ¾ A in this example.
Best Answer
Lets put some numbers on "is well away from the (analog) devices that are noise sensitive"
Above is a simulation using default 14mm trace between sensor and Gain#1 (40db) and 14mm trace between Gain#1 and Gain#2 (34dB). Sensor provides 1 milliVoltPP. The OpAmps are OPA211 models (UGBW, Rnoise, Rout, DCgain) with 1nanoVolt noise density. With the selected Hfield aggressor (a switching regulator located 10mm away from the 2 traces of the PCB), we have only 2dB SNR. With Gargoyles off (that is, NONE of the 4 classes of interferers active), we have 54dB SNR.
What are your degrees-of-freedom? reduce the magnetic loop area (edit the trace to be shorter) or move the SwitchReg much further away or slow the SR edge rate (efficiency impairment). Here is the trace edit menu:
Some magnetic fields decay as 1/distance, some as 1/log(distance), some as 1/distance^2, etc. At 2MHz switcher clock rate, the PCB foil will attenuate the faster energy in the edges, but the 2MHz fundamental is little affected by Skin Depth. The OpAmps have enough UGBW to let lots of 2MHz energy come through.
EDIT At present, the prediction of HFI --- magnetic field interference --- by Signal Chain Explorer uses the infinite-wire-to-small-loop model: $$Vinduce = [MUo * MUr * Area/(2*pi*Distance)] * dI/dT$$
For air/vacuum/copper, this simplifies to $$2e-7*Area/Distance * dI/dT$$
A MCU clock line, swinging 5 volts in 5 nanoseconds while charging 20pF, needs current (I = C * dV/dt) of 20e-12 * 1v/1ns = 0.020 amps (probably 0.040 amps peak), with a triangular buildup and decay of current through all the MCU package and PCB inductances. What will 0.04 amps peak, rising in 2.5 nanoseconds, induce 1cm away into a 1cm^2 loop. (for easy math, use 2.0nS Trise)
Vinduce = 2e-7 * 0.01 meter * 0.01meter/0.01meter * 0.04amps/2nS
Vinduce = 2e-7 * 1e-2 * 1amp/50 nanoseconds (20amp/uS, or 20e6) = 2e-9 * 20e+6
Vinduce = 40e-3 = 40 milliVolts.
This decays only linearly with distance. However, the fast edge (2 or 2.5ns) should be strongly attenuated by any intervening copper sheets/planes, with skin depth being your friend.
Below is the HFI database (used if Gargoyles & HFI & I/C{enables trace model} are clicked); I've deselected the SwitchReg, and selected/saved the MCU clock.