Electronic – Confusion: Lock range of PLL


Suppose we have a type-I PLL whose block diagram is shown below:
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Here \$k_{pd}\$ is the average gain of the phase detector producing the control voltage \$V_c\$ which is input to the Voltage Controlled oscillator (VCO). In the feedback path we have a frequency divider which divides its input frequency by N.
Suppose input frequency is given by \$\omega_{ref} (=2\pi*f_{ref})\$ and output frequency is \$\omega_{out}\$, then in general the phase difference between the input and the fed-back frequency is given by: \$(\omega_{ref} – \omega_{out}/N)t + \Phi_{ref} – \Phi_{out}/N\$.This error signal is input to the phase detector. The steady state phase difference should be given by: \$\Phi_{ref} – \Phi_{out}\$ with \$\omega_{ref} = \omega_{out}/N\$. Does, this frequency relationship hold true even if \$ |\Phi_{ref} – \Phi_{out}| \ge 2\pi\$, which is beyond the range where the PLL will get locked?
In other words, does the frequency relationship between input and output (\$\omega_{ref} = \omega_{out}/N\$) maintained even if the PLL doesn't get locked? If not, what happens to the output signal (in steady state) if PLL is beyond the lock range (given by \$ |\Phi_{ref} – \Phi_{out}| \ge 2\pi\$)?

Best Answer

If input frequency and feedback frequency (after dividing) are the same then the PLL is potentially going to fall into a state of in-lock because the phase detector doesn't care about phase differences that are multiples of 2\$\pi\$: -

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As the "wandering" clock leaves perfect phase alignment with the static clock (left side), the EXOR output starts to produce thin pulses that become wider as the the wandering clock leads the static clock by greater amounts. At perfect anti-phase between the two clocks the EXOR output is a constant "1" and as the leading extends even more, the EXOR output repeats itself as the phase difference between wandering clock and static clock is 2\$\pi\$ (right side).