Electronic – contribution statements in verilog-A

The warning is basically suggesting that you use an explicit clock primitive, which for whatever reason isn't inferred automatically by the tools.

There should be a reference for your particular FPGA that tells what primitives are available. For a Spartan3E, for example, Xilinx UG617 describes the BUFGCE primitive ("Global Clock Buffer with Clock Enable") and shows how to instantiate it. Other vendors will have similar documentation.

Your clock distortion is probably occurring because tristating an output line isn't something that can be done instantly. Whatever is being driven has both inductance and capacitance, so even if the driver could go high-Z in zero real time (which it can't), the driven network will continue to ring for some time. If that's a problem, you would need to find a way to ensure that the clock line is low, and has been for some time, before tristating it. All in all, there is probably a better way to accomplish your goal besides tristating a clock.

First, note that not all Verilog designs are synthesizable. Usually, only a very specific subset of constructs can be used in a design that is to be realized in hardware.

One important restriction that pops up is that every reg variable can only be assigned to in at most one always statement. In other words, regs have affinity to always blocks.

The following types of always blocks can generally be used.

always @(*) begin
    // combinational
end

always @(posedge clk) begin
    // sequential
end

In the former case, the * indicates that the block should be executed whenever any signal used in the block changes or, equivalently, that the block should be executed continuously. Therefore, regs that have affinity to combinational always blocks are implemented as signals computed from other signals using combinational logic, i.e. gates.

Registers that have affinity to always blocks of the latter type, on the other hand, are outputs of D flip-flops that are clocked on the rising edge of clk (falling edge if negedge is used). Inputs to the flip-flops are, again, computed with combinational logic from other signals.

Consider the following, somewhat contrived example.

reg out, out_n;
always @(*) begin
    out_n = !out;
end
always @(posedge clk) begin
    out <= !out;
end

Here, out_n is associated with the first always block, out with the second. out_n will be implemented with a single NOT gate that will drive out_n and be driven from out (note that it is a pure combinational logic). On the other hand, out will be driven by a flip-flop clocked from clk. The input to the flip-flop will again be computed by a NOT gate from out (which is driven by the aforementioned flip-flop). Optimizing synthesizers will combine the two NOT gates and use one NOT gate and one flip-flop.

Depending on the hardware you have available, other types of constructs can be used. For example, if the flip-flops have asynchronous resets, the following construct is also synthesizable.

always @(posedge clk or posedge rst) begin
    if (rst)
        // reset
    else
        // sequential
end