asiccmosdigital-logic
Is there any resource/datasheet where I can find the kilogate (kGE) of the various CMOS technologies? Essentially, I have a bunch of ASIC circuits with their areas given in mm2 that I want to convert to kGE for ease of comparison. Does the kGE/mm2 vary from manufacturer to manufacturer or is it constant?
I did find some kGE/ mm2 equivalents given in some document, but the resource it cited is no longer existent so I can't vouch for the values provided.
Thanks for clarification.
To construct the truth table, you need to manually assess each combination. A table works well, hence the name "truth table"! I assume you understand logical ANDs and ORs, to make sense of this answer.
First, you want to solve each ANDed group separately. Boolean algebra has the same order of precedence as standard algebra, with AND treated like multiplication, and OR treated like addition. Put these answers in a table. Don't worry, I'll attach a picture to demonstrate. Once you have all of these statements figured out, then you can OR them together. Follow the red lines on the following table:
Now that the table is completed, you can build a map. One of the standard configurations is shown below. You have two bits defining the columns, and the other two bits defining the rows. Find the square that intersects the binary inputs (A, B, C, and D), and fill in the answer from your truth table. I've done two of them, in Purple and Orange:
I'll leave the rest for you! You didn't ask how to solve the K-Map. I assume you know how?
Take care!
(P.S. I've included a typo in the truth table. Can you find it?)
Consider the circuit diagram in which a CMOS inverter drives a capacitive load.
The delay offered by the inverter is the time taken to charge/discharge the capacitor and is defined as \$\tau = (t_{LH} + t_{HL})/2\$. Where \$t_{LH}\$ is the time required to charge the capacitor. This happens via pMOS transistor and \$t_{LH} = C_{L}R_{p}\$. Similarly, \$t_{HL} = C_{L}R_{n}\$. Where \$R_n\$ and \$R_p\$ are the equivalent resistance of nMOS and pMOS transistors when they are in saturation.
But \$R_p\$ is greater than \$R_n\$ because of the reduced mobility of holes when compared with electrons. Hence low-to-high transition takes more time than high-to-low transition. The width of pMOS is increased so that \$R_p\$ and hence \$t_{LH}\$ and \$\tau\$ can be reduced. Usually pMOS width is made as 2 - 3 times that of nMOS. The most widely used value is 2. Hence making pMOS width 2 times that of nMOS width,
This applies for other gates also. Those gates are sized so as to get same current driving capacity as CMOS inverter. This is done by making the resistance equal to that of inverter by changing the width. 
Figure shows an inverter along with a two input NAND and NOR. So as to make the resistance of gate equal to that of inverter, the width of series transistors are doubled. The widths of transistors in parallel are not changed since we will be taking critical path for delay calculation.
I think this explains your circuit also.
Best Answer
The number of gates per unit area is a function of many parameters, including the particular design rules for each manufacturer. If one manufacturer has more layers of interconnect than another then the effective gate density may be much higher even if the transistor geometry is very similar. The architecture and structure of the chip can also be a factor. For example, chips where a large fraction of the area is devoted to memory will have more transistors per unit area than chips that have complex processors. Manufacturers often assume that four transistors is the equivalent of a gate, which is a pretty crude metric. The bottom line is that comparing different IC manufacturers at a given process node, or the same manufacturer at different process nodes, is not very meaningful.