capacitorcounterltspicemodelingsimulation
I had been using these modeling technique for counting number of clock cycles.
Delay is created and inverted – to get small positive edge of the clock and count numbers is charged based on the number of pulses. But this needs to change value of R2 and C2 and counts are sometimes greater or less than integers.
Is there any other alternatives so that we can count number of clock cycles and reset it?
It sounds like you don't have an external reset signal to respond to, you just want to count to some number then go to zero as the next step. You could consider this a mod n counter, where n is one more than the maximum count in your counter.
So I'm not sure what you mean about "losing a signal" while doing the reset. If you had a 3-digit decimal counter and it rolled over from 999 to 000, you wouldn't consider it as "losing a signal", it would just be counting to the next value in mod-1000 arithmetic.
So if you do
always @(posedge clock) begin
if (counter == some_number) begin
counter <= 0;
end
else begin
counter <= counter + 1;
end
end
You'll have a counter that counts continuously in mod-some_number+1 arithmetic. Alternately you could say it counts to some_number, then resets to zero without ever "losing" a clock pulse.
If some_number+1 happens to be a power of 2, you don't even need the reset condition in your code. For example, for a mod-16 counter, you can just use a 4-bit counter, and the synthesized logic will count continuously and repeatedly from 0 to 15.
The counter, i.e. 4026, that you specify is a device already containing the 7-segment decoder. Plus this counter is not really suitable to the application where you want it to count from 1 through 6.
Instead look at using a counter such as a 74HC161. This can be hooked up as shown below to make it count from 1 through 6.
This circuit will count from up to 6 (i.e. the state where QB and QC both come to 1's in the output count. The 74HC00 NAND gate will detect this condition and force the synchronous LOAD input active low. On the next clock pulse from the 555 chip the counter will reload to a value of 1 (Inputs D C B A in the 0001 binary state) as opposed to advancing to a count of 7. Subsequent clocks will then count 1->2, 2->3, 3->4, 4->5, and 5->6 where the reload cycle will repeat itself.
Note that at initial power up this circuit may have an initial value in QD QC QB and QA that is outside of the range of 1->6. If this happens it is just necessary to let the clock run till the counter advances to a state where QB and QC are both 1's. If this behaviour is unacceptable then is is necessary to design in an additional signal that low ORs in with the output of the NAND gate to initially force the counter LOAD Input low for one or more clocks from the 555.
Best Answer
What you need is a resettable integrator. You have a nice approach, but you should really take time to read the manual, you'd find out that there are quite a few surprises in there.
For example, if an A-device is referenced directly to the ground, you don't need to connect the unused inputs to the 8th pin, they can be left floating. Tying them up to the 8th pin is done internally (i.e. the gate does not act like a real-life case with floating inputs).
Another one is that behavioural
if()expressions introduce discontinuities around the jump and may cause, more often than not,timestep too smallerrors, or similar. You could use abisource, instead of abv, which allows internal parasiticsRpar/Cpar, which give you a time constant which smooths out a bit the sharp transition. The better solution is to use an A-device, which is far superior both in terms of convergence and runtime (the builtin parameters allow for many tweaks).These said, here is a version of a resettable integrator:
A1andA2form the integrator, driven by the complementary clocks generated byA4. Thetauis neded to allow for smooth rise/fall times whose trigger points for the two S&Hs fall after the trigger point of the input signal. This can be done with settingrefin the S&H, but this way is clearer and also affects both S&Hs at once.A2receives the output ofA1on its inverting input, so that the output can go back intoA1's inverting input, creating the needed positive feedback for an integrator.A3is amota(multiplying OTA) that takes care of the reset function (active low). The reset signal should be strictly0 Vor1 V, sinceA3is a multiplier. If the external signal is not with these limits, it can be adjusted by either an A-device gate, or by theu(), orbuf()(or invertinginv()) functions.A few things to notice: LTspice's S&H has a default upper/lower limit of +/-10 V, which don't act as hard limits, rather they attenuate by a factor of 1000 (or so) everything going beyond the limits. This means that a
1001 Vinput and a limit ofvhigh=1will result in a2 Voutput, not1 V. The 2nd S&H hasvlowset, because it's in an inverting configuration.A3has thelinearflag, which makes its output to vary linearly untilvhigh/vlow, after which, similar to its S&H cousin (both A-devices), it does not hard-limit the output, rather it attenuates by a factor of around 2 (same link as for the S&H). Lastly, the output starts from 1, since it's considered that a trigger can only come after a pulse, but if this behaviour is not wanted, add a current source of1 mAat the output, drawing current to the ground. This, combined with the default output resistance for the S&H A-devices of1 kOhm(an exception to the rest of the A-devices, can be changed by settingrout), creates a-1 Vvoltage that is subtracted from the output.