Electronic – DDR4 pull-up resistors and decoupling clock lines

• TTL has a threshold between low and high that is closer to ground than to the positive rail, so it is better when the stronger transistor pulls the output down against the relatively weaker resistor.

• In general ground is presumably a better (e.g. more stable) reference voltage than a power rail.

• You can use open collector/drain outputs as voltage converters, if you connect the resistor to the positive rail of the target voltage.

• The ancient resistor transistor logic even used this as its working principle throughout.

That said, some microcontrollers have configurable internal pull-ups and pull-downs, e.g. the NXP LPC1xxx.

This is an SRAM-based FPGA. After cycling power, its configuration is lost!

Normally a board using these FPGAs will have some non-volatile memory, and you load the configuration into that. The FPGA has some logic (configured by M0,M1,M2 the Configuration Mode pins) to boot itself from several common types of Flash memory or EEPROM. Some of them fit into the JTAG chain so you can program them with Impact and the Platform Cable you have.

I can't help with the precise details, the XC2S100 is a rather old device, but Xilinx have plenty of documentation on configuration memory.

Meanwhile, you can continue your experiments configuring the FPGA directly, in the knowledge that this is the normal behaviour for this FPGA.

This may seem odd, and there are indeed a few non-volatile FPGAs; ACTEL (Microsemi) make some. But SRAM technology is such a good match for FPGA logic that it makes sense despite the obvious drawbacks.

The non-volatile FPGAs are a compromise : relatively small and relatively slow - so much so that for most applications, the inconvenience of an an external ROM is a small price to pay for the advantages of SRAM-based FPGAs.