capacitordecoupling-capacitorintegrated-circuit
I understand that decoupling capacitors are small capacitors (often 100nF) used on VCC/VDD on ICs. When are they most required and when is it just silly using them on every IC.
Second question first -
2 x 680 uF often will have a better ripple current rating than a single larger cap - sometimes very significantly so.
2 x 680 uF also may be lower height or easier to fit in board space - MAY have more area but be less obstructive than a single larger cap.
Also, as you say, ESR may be better, but often a single large cap is as good.
The 0.1 uF capacitor is intended to remove very high frequency components better than the larger capacitors do.
The small capacitor will usually have have low ESR, low lead and internal inductance, a higher self resonant frequency and a lower overall impedance at higher frequencies. At least, that's the plan. Reputable manufacturers may publish tables showing impedance with frequency and from these an excessively keen [tm] designer can provide a filtering combinatuon that produces a best overall result. It was tradional to consider a 0.1uF cap as the standard HF filter cap but there have been two schools of though to that in recent times.
One argument is that increasing frequencies of both smps and processors and target ICs make smaller caps better suited to the typical frequencies. The other holds that the new ceramic caps are far superior to those of eg adecade ago and that a 1uF or even a 10 uF ceramic will do a fine job at relevant frequencies. Both arguments have merit. If you use a 0.1 uF moderm ceramic instead of going to a 1 uF then you arguably get the benefit of both arguments :-). (ie it's bigger than you might have used and smaller than you might have used).
I do not see at a quick read anything that says where that capacitor is physically located. While the caps are shown sequentially on the diagram, that is only an electrical diagram and actual layout is not strongly suggested by it. General component placement will often have some reseblance to circuit diagram flow but nothing is necessarily fixed. In this case the 0.1uF can be phyically near the cathode of D1 and the ground side of R2 R14 R16 and that is where I would try to locate it.
Cypress excellent - Using decoupling caps
How to select bypass caps Goodish
Tends to suggest that bigger is better mostly :-) :
From this excellent guide - A practical guide to high speed PCBB layout
Useful and related but not 100% on topic here Useful
Related - caps and ESR Wikipedia
The most likely reason why that is done is because, in real life, capacitors do not have infinite bandwidth. Generally, the higher the capacitance of the capacitor, the less it will be able to react to high frequencies, while small-valued capacitors react better to higher frequencies, as seen in the graph below. Using two different-valued capacitors together is just done to improve the response of the filtering.
Best Answer
First, visit this prior answer on how capacitors in parallel will resonate.
Bypass capacitor vs low-pass filter
In circuit design, whether discrete or onchip, we assume the proposed/desired functionality (gain of 140, up to 4.5MHz, with limiting of the FM TV Audio, for example) will be achieved.
Yet we throw these circuits with enormous gain-bandwidth onto white boards with 10s or 100s of nanoHenries inductance in the 'ground' and in the 'power' leads, and are surprised by some squirrely behaviors, perhaps only showing up at cold temperatures.
Here is an example of the risk:
simulate this circuit – Schematic created using CircuitLab
Notice the Iload flows back into the Amplifier thru the SINGLE GROUND pin, which has inductance.
Given the input signal (Vin+) is grounded, we may wonder what is going on. However, that input signal is between Vin+ and Vin-, which is tied to the Return path of the high output current.
Which is on the top of an inductor, thus that "input signal" will be rising as the frequency rises.
At some high frequency, that Vground (or the Vin-) will be large enough to cause oscillation.
Let's run the math:
Vout = Vin * Gain (and we assume Gain is flat, for easy derivation)
Vin = Lgnd * d(Iground)/dT
Iground = Vout/Rload
Vin = Lground * d(Vout/Rload)/dT
and assume Vin and Vout are sinusoids, thus
Vin = Lground/Rload * d(Vout*sin(2*pi* Freq *time))/dT
Vin = Lground/Rload * Vout * 2 * pi * Freq *cosine(2 * pi * Freq * time)
and picking the peak amplitude, we have
Vin = Lground/Rload * Vout*2*pi*Freq
and we can replace Vout by Vin * Gain, to find
Vin = Lground/Rload * Vin * Gain * 2*pi*Freq
So we manipulate this, to find
1 = Lground/Rload * Gain *2*pi*Freq, and now solve for Freq(of oscillation)
Rload/(2*pi* Lground *Gain) = Frequency of oscillation
What is the frequency (of possible oscillation, ignoring phase shift) if Rload = 50 ohms and Lground is 10nH and Gain = 1 ???
Frequency = 50 / ( 6.28 * 10nH* 1) = 50 / 63nano
Frequency ~~ 800 Megahertz
Which means what?
That RF transmitters should have differential outputs.
===========================================
Suppose you have gain of 10,000 (Flat) and 100nanoHenry inductance, and 1Kohm resistance.
What is your risk of oscillation?
Fosc = Rload / (6.3 * Av * Ground Inductance)
Fosc = 1,000 / (6.3 * 10,000 * 0.1uH)
Fosc = 159 / (10,000 * 1e-7) = 159 / 1e-3 = 159KHz
How does the designer prevent this?
By keeping Load Currents away from the inputs.
By using Bypass Capacitors. By using multiple stages.
==================================
Sometimes two capacitors in parallel will resonant. Plan to dampen them.
What is the application of capacitor between Vcc and GND