Electronic – Dedicated digital filter

There is great flexibility in the design of a digital filter. You can design digital filters that behave very similarly to analogue filters (as Andy aka described). You can also build digital filters than can be hard to reproduce in analogue such as a Linear phase filter or a Half-Band filter. Or non-linear digital filters such as Median filters that have no analogue equivalence in LTI systems.

For your requirements of "a sharp, low pass filter" I'd suggest a simple IIR of the form:

out = (1-a)in + aout

the closer 'a' is to 1 the lower the cutoff frequency of your filter.

You may well have a problem with the 1MHz sample rate and 5Hz cutoff because: a = exp(-2*pi*f/fs) where f is the cutoff frequency and fs is the sample frequency. So for your example:

a= exp(-2*pi*5/1E6) = 0.99997

If you really do need a 1MHz sample rate (because your data must be sampled by a 1MSPS ADC for example), then a 3 stage multi-rate filter is more appropriate. For this you would:

1. Average 32 values at 1MHz and output one sample out of 32 at 1MHz/32
2. Average 32 values at 1MHz/32 and output one sample out of 32 at 1MHz/32^2 (1MHz/1024)
3. Implement an LPF as above with a 1MHz/1024 sample rate.

UPDATE BASED ON NEW INFO FROM OP: Based on your information that:

1. You are interested only in DC
2. You are not sure about the cutoff frequency because you mention 60Hz and 6kHz bandwidth but also "A cutoff frequency of 5Hz"
3. You need flexibility in sample rate

I think your best choice is a CIC Decimator.

Basically, its an MA (FIR) digital filter, made up of

1. an integrator at the input clocked at the ADC sample rate (36kHz shown),

2. a differentiator at the output clocked at the output rate.

   You can control how much filtering you get by changing the output rate.

For example with an input rate of 36kHz and an output rate of 5Hz this gives you a 36000/5 = 7200 point moving average. In reality you'd like to keep the rates as binary ratios so M=13 gives 36kHz in 36kHz/2^13 out and MA length is 2^M = 8192

The group delay of this will be 2^(M-1)/Fin or 113ms for the above example. That's one of the disadvantages of such a simple circuit but would not be a problem in a system whose DC value varies slowly.

Here is a circuit which only lets through pulses with a repetition frequency of less than 1KHz.

When triggered by the leading edge of each input pulse, Monostable IC1 generates a 1ms pulse which clocks D F/F IC3's output high. IC3 is reset when the input pulse goes low again, so the output follows the input. If the frequency is higher than 1KHz then IC1 is continuously triggered and doesn't produce any clock pulses, so IC3 stays in reset.

R2, C2 and IC2B provide a short delay to ensure that IC3 is out of reset when it receives the clock pulse from IC1.

BTW this circuit can be simplified down to just one IC by configuring the other half of the CD4528 as a basic flip-flop. Connect pins 15 and 14 to GND, pin 11 to Vdd, apply clock input (from pin 6) to pin 12, and connect the input frequency direct to pin 4 (+TR) and pin 13 (/RESET). Output is on pin 10.